Memristor-based memory technology is one of the emerging technologies, which a potential candidate to replace traditional memories. Efficient test solutions are required enable quality and reliability such products. In previous works, fault models caused by open, short bridge defects parametric variations during fabrication. However, these cannot describe that cause state faulty cell an undefined state. this paper, we analyze different effects aggregate their behavior into new models,...

Abstract Fast radio bursts (FRBs) are highly energetic millisecond-duration astrophysical phenomena typically categorized as repeaters or nonrepeaters. However, observational limitations may result in misclassifications, potentially leading to a higher proportion of than currently identified. In this study, we leverage unsupervised machine learning techniques classify FRBs using data from the CHIME/FRB catalogs, including both first catalog and recent repeater catalog. By employing Uniform...

As an attractive option of future non-volatile memories, resistive RAM (RRAM) has attracted more attentions. Among RRAM architectures, one transistor memristor (1T1R) cross-bar is the most fledged one. A March C*-1T1R algorithm proposed for 1T1R cross-bar. The pass–fail fault dictionary test analysed. Analytical results show that can detect all modelled faults caused by parametric variation memristors, transistors and their interconnecting wires with a little time overhead compared previous methods.

Recently, the measurements of baryon acoustic oscillations (BAO) by Dark Energy Spectroscopic Instrument (DESI) indicate a potential deviation from standard $\Lambda$CDM model. Some studies suggest that data points luminous red galaxies (LRG) survey in DESI BAO may contribute to this discrepancy. In work, our main goal is investigate whether caused parameterization equation state (EoS) dark energy (DE). Hence, we have examined four popular parameterized models analysis:...

Among resistive random access memory (RRAM) architectures, one transistor memristor (1T1R) crossbar is the most fledged one. For 1T1R crossbar, a logic operation‐based Design for Testability and parallel test algorithm, which an improvement of March C*‐1T1R are proposed. The pass‐fail fault dictionary proposed algorithm analysed. Analytical results show that can detect all modelled faults caused by parametric variation memristors traditional RAM. Compared with MOM, C* C*‐1T1R, time reduced...

In recent years, the Internet of Things (IOT) has been developed very fast. Lots applications have emerged in field IOT. However, most them are independent. this paper, a public and unified platform based on Google Map to integrate those GEO-related IOT is designed implemented. The combination software hardware. part, server included three functional parts hardware different communication ways between real things supported. Finally, Remote Digital Home Control system implemented added our...

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. Due to its high density and low power, one memristor (1R) crossbar is a dominant RRAM structure. In this paper, we propose logic operation-based design for testability (DFT) architecture 1R testing. architecture, memristor-aided (MAGIC) NOR gates are embedded check whether all the cells in 0 s or not at time. A March-like test algorithm also presented proposed...

AbstractAn effective logic built-in self-test scheme aiming at reducing the area overhead of IC testing and improving fault average is proposed, which combines strategies linear feedback shift register (LFSR)-reseeding with test vectors applied by circuit-under-test itself (TVAC). LFSR-reseeding technology first to decrease size set number interior wires, while TVAC stored seeds. An efficient algorithm a modified quick judgment method for path search are proposed. Experimental results ISCAS...

A memristor is regarded as a promising device for modeling synapses in the realization of artificial neural systems its nanoscale size, analog storage properties, low energy and non-volatility. In this letter, an adaptive T-Model network based on CMOS/memristor hybrid design proposed to perform analog-to-digital conversion without oscillations. The circuit composed CMOS neurons synapses. A/D converter (ADC) trained by least mean square (LMS) algorithm. conductance memristors can be adjusted...

In this letter, we present a novel memristor-based restricted Boltzmann machine (RBM) system for training the brain-scale neural network applications. The proposed delicately integrates storage component of neuron outputs and multiply-accumulate (MAC) in memory, allowed operating both them same stage cycle less memory access contrastive divergence (CD) training. Experimental results show that delivers significantly 2770x speedup than 1% accuracy loss against x86-CPU platform on RBM On...

Code-based test vector compressions are the most capable of testing current SOCs consisted a large number IP cores because they do not need structure information cores. However, compression ratios this kind approaches often lower than that other methods, such as linear-decompression-based schemes and broadcast-scan-based schemes. In paper, we propose novel method can greatly improve for code-based techniques with affordable overheads. The decomposes an original set to prominent component...

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate and restore integrity. To evaluate effectiveness proposed adder, an eight-bit demonstrated as study case. Compared to previous standard cell design, reduce 11.1% cells, 22.2% CMOS transistors, 38.9% vias, 58% power. optimized 12.5% 98.1% power, energy.

A new built-in-self-test scheme, referred to as Test Vectors Applied by Circuit-under-Test (TVAC), is proposed in this paper. As the point of view paper, (CUT) no longer only regarded a test object, but also kind available resources. By feedback connecting some CUTpsilas interior nodes input terminals, method can generate set with low area overhead, short application time, and enable at-speed testing. ldquofeedback groupingrdquo search algorithm presented for given CUT its set. The...

CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, be used in a large-scale memory system. In this article, we analyze electrical defects CMOL circuit including open bridge. A parallel March-like test algorithm is presented for covers faults caused by bridge parametric variations during fabrication. Analysis results show that time proposed reduced significantly compared with enhanced methods...

Memristor-based crossbar array is one of the most promising structure for in-memory computing platforms. In a array, material implication logic (IMPLY) can be performed between different word lines or bit lines. Not-material (N-IMPLY) only This brief demonstrates feasibility execution N-IMPLY lines, followed by an approach gate design in which two logics IMPLY and are integrated into array. Both cells rows columns within crossbar. Six basic Boolean gates implemented utilizing proposed...

Scan chain reordering could be used for test compression by making the corresponding set more easily compressed. However, it may adversely affect scan routing creating very long path and modifying signal delays. The paper proposes a virtual reorder technique which targets on compression. approach simply uses RAM-based module to control orders of cells in circuits. To achieve high compression, can virtually arranged into any order different schemes. It does not do real modification chains,...

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem one memristor (1R) crossbars and limit its power consumption in 1R crossbars, is used as a large-scale system. In this paper, we analyze electrical defects CMOL circuit including open bridge. A parallel March-like test algorithm presented for covers defined faults caused by defects....

An idling scheme of Synchronous Switch Harvesting on Inductor (SSHI) is proposed for piling up output voltage the piezoelectric energy (PE) harvester cycle by cycle, to deal with PE harvester’s low voltage. The rectifier integrates active diodes and a parallel-SSHI technique simple control scheme, therefore has high efficiency. simulation results demonstrate feasibility rectifier, which able extract from ultra-low-voltage harvester.

Resistive random access memory (RRAM) is one of the promising candidates for future universal memory. However, it suffers from serious error rate and endurance problems. Therefore, exploring a technical solution greatly demanded to enhance reduce rate. In this paper, we propose reliable RRAM architecture that includes two reliability modules: correction code (ECC) self-repair modules. The ECC module used detect errors decrease module, which proposed first time RRAM, can get information bits...