Rishu Chaujar

ORCID: 0000-0002-0161-8449
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About
Contact & Profiles
Research Areas
  • Advancements in Semiconductor Devices and Circuit Design
  • Semiconductor materials and devices
  • Nanowire Synthesis and Applications
  • Ferroelectric and Negative Capacitance Devices
  • Silicon Carbide Semiconductor Technologies
  • Integrated Circuits and Semiconductor Failure Analysis
  • GaN-based semiconductor devices and materials
  • Radio Frequency Integrated Circuit Design
  • Thin-Film Transistor Technologies
  • Perovskite Materials and Applications
  • Silicon and Solar Cell Technologies
  • Semiconductor Quantum Structures and Devices
  • Semiconductor materials and interfaces
  • Conducting polymers and applications
  • ZnO doping and properties
  • Analytical Chemistry and Sensors
  • Chalcogenide Semiconductor Thin Films
  • Ga2O3 and related materials
  • solar cell performance optimization
  • Organic Electronics and Photovoltaics
  • 2D Materials and Applications
  • MXene and MAX Phase Materials
  • Acoustic Wave Resonator Technologies
  • Functional Brain Connectivity Studies
  • Electrostatic Discharge in Electronics

Delhi Technological University
2016-2025

Jaypee Institute of Information Technology
2019

Institute of Applied Physics
2018

National Yang Ming Chiao Tung University
2017

University of Delhi
2007-2010

Deen Dayal Upadhyay Hospital
2008-2010

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive charges) and acceptor (negative charges), present at Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, on analog/RF performance linearity distortion analysis heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance tunneling current TFET. Various figures merit such...

10.1109/tdmr.2016.2564448 article EN IEEE Transactions on Device and Materials Reliability 2016-05-06

This paper investigates the reliability of PINgate-all-around (GAA)-tunnel field-effect transistor (TFET) with N± source pocket. The PNIN-GAA-TFET is examined by analyzing: 1) impact interface trap charge (ITC) density and polarity 2) temperature affect ability on analog/RF performance device. It realized that traps existing at Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> modifies flatband voltage and, thereby, alters analog RF...

10.1109/ted.2017.2670603 article EN IEEE Transactions on Electron Devices 2017-03-07

This work investigates how interface trap charges (ITCs) affect the performance of biosensors made from junctionless nanowire field‐effect transistors (NWFETs) with triple hybrid metal gate dielectric modulated gates. The subthreshold sensitivity double and silicon NWFET was investigated using SILVACO ATLAS‐TCAD simulation tool, emphasizing impacts positive negative ITCs. Simulations examined impact uniformly immobilized biomolecules within nanogap cavity region evaluated key electrical...

10.1155/acmp/3744806 article EN cc-by Advances in Condensed Matter Physics 2025-01-01

In this paper, analog/RF performance and small signal behavior of Transparent Gate Recessed Channel (TGRC) MOSFET has been investigated in terms transconductance, DIBL, channel resistance parasitic capacitances, cut-off frequency maximum oscillator frequency. Results so obtained are compared with Conventional (CRC) at THz range, using ATLAS-3D device simulator. Furthermore, the impact technology parameter variations gate length (Lg) also evaluated. Result shows that there is 42% enhancement...

10.1016/j.mejo.2015.12.007 article EN Microelectronics Journal 2016-01-18

In this paper, reliability issues of In2O5Sn (indium-tin oxide: a transparent material) gate recessed channel (TGRC)-MOSFET has been analyzed by considering the effect interface trap charges (both positive and negative) present at Si/SiO2 interface. Following device, characteristics are studied in terms static, linearity, intermodulation figure merits. It is found that with amalgamation indium tin oxide on conventional recesses (CRC) MOSFET, it exhibits improved immunity against comparison...

10.1109/ted.2018.2793853 article EN IEEE Transactions on Electron Devices 2018-01-31

In this paper, the temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET (HD GAA TFET) has been addressed, and results are simultaneously compared with around tunnel (GAA TFET). This is done by investigating effect interface trap charges such as donor (positive charges) acceptor (negative at various operating temperatures on device analog parameters RF figure merits. It observed that, high bias, TFET exhibits weak dependence owing to band...

10.1109/tnano.2017.2650209 article EN IEEE Transactions on Nanotechnology 2017-01-09

10.1007/s10854-020-04216-7 article EN Journal of Materials Science Materials in Electronics 2020-08-31
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