<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows sub-60-mV/dec SS in silicon-based TFETs. Based on simulation results, gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 70 nm, respectively. However, <emphasis...

A tunneling field-effect transistor (TFET) is considered one of the most promising alternatives to a metal–oxide–semiconductor due its immunity short-channel effects. However, TFETs have suffered from low <emphasis emphasistype="smcaps" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</emphasis> -current, severe ambipolar behavior, and gradual transition between - xmlns:xlink="http://www.w3.org/1999/xlink">off </emphasis> -states. To address those...

An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for first time. It more scalable than other vertical-BTBT-based TFET designs and provides <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1000\times $ </tex-math></inline-formula> higher ON-current ( notation="LaTeX">$I_{{\mathrm{\scriptscriptstyle ON}}}$ ) a...

Because of the "Boltzmann tyranny" (i.e., nonscalability thermal voltage), a certain minimum gate voltage in metal–oxide–semiconductor (MOS) devices is required for 10-fold increase drain-to-source current. The subthreshold slope (SS) MOS is, at best, 60 mV/decade 300 K. Negative capacitance organic/ferroelectric materials proposed order to address this physical limitation technology. Here, we experimentally demonstrate steep switching behavior device—that SS ∼ 18 (much less than mV/decade)...

This paper proposes the novel concept of an optically invisible antenna built using photolithography that can be integrated in active display panels such as organic light emitting diodes and liquid crystal displays. Represented antenna-on-display (AoD), this proposed approach is exemplified for future millimeter-wave (mmWave) 5G cellular devices. Empirical examinations confirm devised diamond-grid-shaped 2000 Å-thick Ag-alloy electrodes on a glass substrate feature electrical loss...

Oxygen vacancies and adsorbed oxygen species on metal oxide surfaces play important roles in various fields. However, existing methods for manipulating surface require severe settings are ineffective repetitive manipulation. We present a method to manipulate the amount of by modifying adsorption energy electrically controlling electron concentration oxide. The control ability is verified using first-principles calculations based density functional theory (DFT), X-ray photoelectron...

Abstract This study implements a highly uniform 3D vertically stack resistive random‐access memory (VRRAM) with four‐layer contact hole structure. The fabrication process of VRRAM is demonstrated, and its physical electrical properties are thoroughly examined. X‐ray photoelectron spectroscopy transmission electron microscopy employed to analyze the chemical distribution structure device. Multilevel capability, reliable endurance (&gt;10 4 cycles), retention (10 s) successfully obtained....

This paper suggests the practical implications of utilizing a high-density crossbar array with self-compliance (SC) at conductive filament (CF) formation stage. By limiting excessive growth CF, SC functions enable operation without access transistors. An AlOx/TiOy, internal overshoot limitation structure, allows to have resistive random-access memory. In addition, an overshoot-limited memristor makes it possible implement vector-matrix multiplication (VMM) capability in neuromorphic systems....

The design of gate-all-around (GAA) MOSFETs was optimized and compared with that double-gate MOSFETs. We discussed the optimal ratio fin width to gate length investigated short-channel effects GAA Using three-dimensional simulations, we confirmed were properly suppressed although same as in Finally, cubical channel cylindrical-channel ones. As a result, it observed latter showed maximized up 1.2.

This letter discusses the effects of device geometry, such as channel layer thickness and multiple-gate structure on hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). According to simulation results, contrary conventional TFETs or MOSFETs, HG show improved subthreshold swing <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$(SS)$</tex></formula> for increasing decreasing number...

In this work, novel L-shaped tunneling field-effect transistors (TFETs) have been proposed. The proposed TFETs feature higher on-current ( I on ) and lower subthreshold swing SS than conventional TFETs. It is because large cross-sectional area of band-to-band junction which perpendicular to the channel direction their barrier width W t defined by length an intrinsic silicon region. As devices are based Si without any other material, it can be fabricated with well-established process...

The ambipolar behavior of tunneling fieldeffect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (ν). It found that the malfunction TFET can result from state which is not on- or off- state. Therefore, effect on device performance should be parameterized quantitatively, and this successfully evaluated as function structure, gate oxide thickness, supply voltage, drain doping concentration body using ν.

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one requirements, there have many researches about novel devices consumption. Though scaling supply voltage is effective way consumption, degradation occurred metal–oxide–semiconductor field-effect transistors (MOSFETs) when reduced because subthreshold swing (SS) MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis,...

The work-function variation (WFV) effects of tunneling field-effect transistors (TFETs) are discussed for the first time. According to 3-D device simulation results, TFETs less immune WFV than metal–oxide–semiconductor FETs (MOSFETs) in terms subthreshold swing <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$(S)$</tex></formula> and threshold voltage xmlns:xlink="http://www.w3.org/1999/xlink"><tex...

We have fabricated a 100-nm n-/p-channel I-MOS by adopting novel structure. The proposed structure shows some advantages over the conventional one in terms of self-alignment and reduced number photolithography masks. It leads to low fabrication cost, accelerated scaling down, enhanced performance due parasitic elements. normal transistor operation with small subthreshold swing less than 11.8 mV/dec at room temperature. n- p-channel an ON/OFF current 81.1/2.8 78.2/3.4 μA per μm, respectively....

70-nm I-MOS devices have been integrated with TFETs for the first time by adopting a novel process method. The integration of device TFET is meaningful in that it compensates weak points each and implements both high-performance low-power functionality on same substrate. Additionally, using SOI substrate modifying mask layout, ON/OFF current ratio increased dramatically factor more than 1000 compared our previous works. Finally, we investigated applicability to inverter 6T-SRAM cell...

The influence of inversion layer on tunneling field-effect transistors (TFETs) has been investigated. Simulation results show that drain current <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(I_{D})$</tex></formula> saturation is related to formation. Surface channel potential Notation="TeX">$(\Psi_{S})$ </tex></formula> pinning due the formation makes Notation="TeX">$I_{D}$</tex> </formula> less...

Abstract Smart healthcare systems integrated with advanced deep neural networks enable real‐time health monitoring, early disease detection, and personalized treatment. In this work, a novel 3D AND‐type flash memory array rounded double channel for computing‐in‐memory (CIM) architecture to overcome the limitations of conventional smart systems: necessity high area energy efficiency while maintaining classification accuracy is proposed. The fabricated array, characterized by low‐power...

A new electro-mechanical non-volatile memory (NVM) cell design is proposed and demonstrated for the first time. The fabricated cells operate with relatively low program/erase voltages large sensing margin. Because only dielectric metal layers are required, this suitable post-CMOS fabrication. As area reduced, operating can be maintained by scaling vertical dimensions of cell. Nanometer-scale technology therefore attractive high-density embedded applications.

Hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) with dual-dielectric-constant (k) spacers have been fabricated and characterized. They a heterogeneous gate dielectric layer which consists of high-k material (HfO2) SiO2 at the source drain side, respectively. The dual-k spacer has an inner outer spacer. dual-k-spacer HG TFETs show higher on/off current ratio, on-current better subthreshold slope than control use only for Moreover, impact length inserted under (Lhigh-k)...

Monolithic three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated. This is the first experimental demonstration of 65-nm M3D CMOS-NEM RL satisfying 1.2-V supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\mathsf {DD}}$ </tex-math></inline-formula> ) requirement technology node. The fabrication process identical to...

By utilizing the dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> spacer (DS) technique, a novel structure has been proposed to improve thermal characteristics and ON-current ( notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}{)}$ in gate-all-around (GAA) MOSFETs. The GAA MOSFET utilizes DS, which contains aluminum oxide (Al2O3) as an inner so that...

Artificial olfactory systems (AOSs) that mimic biological are of great interest. However, most existing AOSs suffer from high energy consumption levels and latency issues due to data conversion transmission. In this work, an energy- area-efficient AOS based on near-sensor computing is proposed. The efficiently integrates array sensing units (merged field effect transistor (FET)-type gas sensors amplifier circuits) AND-type nonvolatile memory (NVM) array. signals the directly connected NVM...

Abstract There is a need to design hardware synapse array appropriate for enhancing the efficiency of neuromorphic computing systems while minimizing energy consumption. This study introduces memristor device with an AlO x overshoot suppression layer (A‐OSL) achieve self‐compliance effect. By optimizing each cell within 16 × crossbar array, synaptic devices are successfully fabricated reliable characteristics and 3‐bit multilevel capabilities. In addition, oxygen composition TiO annealing...