A contact resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{c}$ </tex-math></inline-formula> ) becomes a major parasitic in highly scaled modern semiconductor devices. wrap-around (WAC) has been suggested as promising solution to reduce the , because its area is larger than that for conventional top (TC) structure. Therefore, this article, electrical and thermal characteristics are widely...

The realization of a Negative Capacitance (NC) phenomenon in TCAD, considering several realistic aspects transport physics, remains challenging. In this paper, we investigated the aging and reliability NC-FinFET self-heating effect (SHE) interface trap charges with varying concentration energy location. general, FEPolarization hydrodynamic models cannot be coupled at same simulation flow; thus, employed iterative approach. Due to SHE, lattice temperature increases, which impacts Landau...

For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists of hafnium dioxide (HfO2) and silicon (SiO2), which has high thermal conductivity, hence SHEs are improved. In order to validate the HGD, technology computer-aided design (TCAD) simulation performed through Synopsys Sentaurus three-dimensional (3D) tool. As a result, when adopted GAA MOSFETs, can be...

In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The SRAM developed by incorporating bottom-up approach (from device level to level). device/circuit utilizes high conductivity permittivity of titanium dioxide (TiO2). Specifically, TiO2-based vertically stacked nanosheet field-effect transistor (NSFET) in the shows improvement maximum lattice temperature ( <inline-formula...

By utilizing the dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> spacer (DS) technique, a novel structure has been proposed to improve thermal characteristics and ON-current ( notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}{)}$ in gate-all-around (GAA) MOSFETs. The GAA MOSFET utilizes DS, which contains aluminum oxide (Al2O3) as an inner so that...

Nanosheet Field Effect Transistor (NSFET) has emerged as a promising candidate to replace FinFET devices at sub-7nm technology nodes and for different SoC applications. In this work, we have investigated the DC properties of 3D vertically-stacked NSFET including impact self-heating effect (SHE) also influence geometry scaling. The thermal resistance maximum lattice temperature been analyzed according device’s channel number. Also, distribution exposed. During investigation, it observed that...

Internal and external process variations severely affect the device threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{th}})$</tex> and, in turn, device's reliability. For first time, this paper presented a thorough analysis of self-heating aware xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{th}}$</tex> variation Nanosheet FET thus, aging. Using well-calibrated TCAD models, we evaluated 'change...

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity heterogeneous interfaces suggest that performance may be severely limited by self-heating, especially at higher power device densities. Here, we investigate the high-field breakdown of amorphous indium tin (ITO) scanning microscopy (SThM) multiphysics simulations. The ITO devices break irreversibly channel temperatures ~180...

Amorphous oxide semiconductors are gaining interest for logic and memory transistors compatible with low-temperature fabrication. However, their low thermal conductivity heterogeneous interfaces suggest that performance may be severely limited by self-heating, especially at higher power device densities. Here, we investigate the high-field breakdown of ultrathin (∼4 nm) amorphous indium tin (ITO) scanning microscopy (SThM) multiphysics simulations. The ITO devices break irreversibly channel...

The high integration of integrated circuit (IC) chip design has made thermal-aware as one the first priorities modern IC industry. Even though technologies have aimed to achieve thermal stability by optimizing design, rapidly growing requires not only in level but also transistor level. Such with bottom-up (from packaging level) can be used reliable chips. Moreover, since aluminum oxide (Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>...

Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO2) possessing ferroelectric properties. This material is of special interest since it based on lead-free, simple binary HfO2, and has excellent endurance property (1 × 109 field cycles without fatigue. There exists substantial information about the aspects La:HfO2 but lacks proven application potential for CMOS-compatible low-power memory design. In this work, 10 % La metal cation fraction HfO2 proposed as gate stack...

In this paper, we proposed Omega-Shaped-Gate Nanowire Field Effect Transistor (ONWFET) with different gate coverage ratio (GCR). order to investigate electrical and self-heating characteristics of the devices, on-current, off-current, subthreshold swing (SS), operating temperature were examined by using 3D TCAD simulator compared nanowire MOSFET (NW-MOSFET). As a result, possibility reducing off-current was demonstrated ONWFET 40% GCR. Therefore, can save power consumption serve as low...

In this paper, an investigation is performed to analyze the L-shaped tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV) with help of technology computer-aided design (TCAD) simulation. Depending voltage, three variations occur in transfer curves. The first one on-state current (ION) variation, second hump (IHUMP) and last ambipolar (IAMB) variation. According simulation results, ION sensitive size tunneling region could be reduced by increasing region....

In this research, we propose an Integrate-and-fire (I&F) Silicon-on-insulator (SOI) neuron circuit incorporating a Schmitt trigger as action potential generating component. The is composed of four MOSFETs, and it presents hysteresis by controlling the threshold one MOSFET using back-gate effect. presented effectively handles input overflow modulating output pulse duration, thus maintaining Rectified-linear-unit (ReLU) equivalence I&F spiking neuron. effect handling modulation was further...

In this article, a reliable drain-extended (De) fin-shaped field-effect transistor (DeFinFET) with improved thermal performance and electrical is proposed for high-voltage (HV) system-on-chip (SoC) applications at 10-nm technology nodes. The device structure uses the dual split field plate (DS) technique high conductivity of silicon dioxide (SiO2), which enables significant improvement in DeFinFET. shows an maximum lattice temperature ( <inline-formula...

In this paper, we demonstrate retention improvement in nonvolatile charge-trapping memory cells by tunneling oxide engineering with Al2O3. By utilizing SiO2/Al2O3/SiO2 layers for the oxide, it is shown that threshold voltage window after 10 years significantly improved from 0.78 V to 4.18 through Synopsys Sentaurus technology computer-aided design simulation. addition, incorporating compared using SiO2/Si3N4/SiO2 layers. The relationship between layer thickness and trapped charge emission...

For improving thermal characteristics and on-current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {ON}}$ </tex-math></inline-formula> ) in vertically stacked nanosheet field-effect transistor (NSFET), the effect of parasitic channel height notation="LaTeX">$H_{\mathrm {parasitic}}$ on electrical has been investigated. By increasing , it demonstrated that maximum lattice temperature...