D. Saint-Patrice

ORCID: 0000-0002-7037-7685
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About
Contact & Profiles
Research Areas
  • 3D IC and TSV technologies
  • Photonic and Optical Devices
  • Electronic Packaging and Soldering Technologies
  • Electrowetting and Microfluidic Technologies
  • Semiconductor Lasers and Optical Devices
  • Advanced MEMS and NEMS Technologies
  • Modular Robots and Swarm Intelligence
  • Phase-change materials and chalcogenides
  • Semiconductor materials and devices
  • Adhesion, Friction, and Surface Interactions
  • Metal Forming Simulation Techniques
  • Advanced Surface Polishing Techniques
  • Liquid Crystal Research Advancements
  • Advanced Semiconductor Detectors and Materials
  • Photonic Crystals and Applications
  • Advanced Sensor and Energy Harvesting Materials
  • Advanced Optical Sensing Technologies
  • Optical Coatings and Gratings
  • Manufacturing Process and Optimization
  • Recycling and Waste Management Techniques
  • Optical Network Technologies
  • Biosensors and Analytical Detection
  • Chalcogenide Semiconductor Thin Films
  • Thin-Film Transistor Technologies
  • Integrated Circuits and Semiconductor Failure Analysis

Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2009-2024

Université Grenoble Alpes
2010-2024

CEA LETI
2008-2024

CEA Grenoble
2008-2024

Institut polytechnique de Grenoble
2010-2015

The study presented in this article concerns germanium telluride (GeTe) phase-change material-based switches, actuated via direct heating and arranged through two configurations: series or shunt. It is concluded that provides a performing solution for GeTe amorphization, preventing heater aging. configurations are compared terms of RF performance, power handling, linearity. Some design rules derived from empirical data, consolidated with thermal simulations. In either configuration, large,...

10.1109/tmtt.2019.2946145 article EN IEEE Transactions on Microwave Theory and Techniques 2019-10-31

Silicon photonics technology is now gaining maturity with increasing levels of design complexity from devices to large photonic integrated circuits. Close integration control electronics 3D assembly and CMOS opens the way high-performance computing architectures partitioned in chiplets connected by optical NoC on silicon interposers. In this paper, we give an overview our works links for manycore systems, low-level high-level system optimization communications. We detail POPSTAR topology...

10.23919/date48585.2020.9116214 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2020-03-01

For heterogeneous materials assembly, the thermal expansion mismatch between chip and substrate is a roadblock for flip bonding of ultrafine-pitch ( les 10 mum) large diagonal devices ges 20 mm). Residual strains in bumps device warpage have been calculated to evaluate thermomechanical limits conventional soldering process using micro bumping. As solution overcome these limits, this paper describes new patented flip-chip technology representing technological breakthrough compared methods...

10.1109/tcapt.2008.2005099 article EN IEEE Transactions on Components and Packaging Technologies 2009-01-30

A low cost packaging solution has been successfully implemented on RF MEMS switches. The encapsulation is made at wafer level by thin film packaging, it allows keeping very small footprint for the device and fully compatible with wire bonding flip chip assembly. In addition to their highly shrinked size, packaged switches excellent microwave performances promising behaviors in terms of reliability, especially redundancy schemes required space applications.

10.1109/transducers.2017.7994016 article EN 2017-06-01

Under bump metallurgies (UBMs) have been assessed in terms of robustness and environmental impact, respectively through aging tests after wafer level balling with SAC305 (Sn 96.5 %, Ag 3 Cu 0.5 % (wt. %)) life cycle assessment (LCA). Three UBMs are considered: Ti 200 nm / Ni 700 Au 100 (UBM A) deposited by sputtering, 2 μm B) electrodeposition (ECD), 10 C) ECD. Configurations A B higher shear strength than configuration C multiple reflows 1000 h at 150 °C high temperature storage (HTS)...

10.1109/ectc51529.2024.00273 article EN 2024-05-28

This paper describes the Wavelens technology: a new type of varifocal liquid lenses actuated by electrostatic parallel plates. The main technological steps involved in fabrication process are discussed and influences membrane material, electrode size composition (rigidity stress) on optical performance evaluated detail. were characterized extensively using wave-front measurements. Optical powers 11m<sup>-1</sup> at 9V (16m<sup>-1</sup> 10V) measured with diameters 3mm. influence power is...

10.1117/12.908057 article EN Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE 2012-01-31

This paper presents the phase change characterization of Germanium Telluride (GeTe) used for RF switches when a direct heating is performed. The study describes method to activate transition between crystalline and amorphous states, allowing reach resistance ratio 1.8.10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> both states. measurements were performed up 40 GHz on fabricated switches, showing an ON-state 1.7 Ω. An OFF-state...

10.1109/imws-amp.2017.8247378 article EN 2021 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP) 2017-09-01

A new type of varifocal liquid lens actuated by electrostatic parallel plates is presented and the main technological steps involved in fabrication process are discussed. The influences membrane material, electrode size optical diameter on performance characterized using wave-front measurements giving basic design rules for device optimization. Optical powers 13m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−1</sup> at 20V 11m 13V measured...

10.1109/transducers.2011.5969719 article EN 2011-06-01

Flip chip is a high-density and highly reliable interconnection technology which mandatory for the fabrication of high end heterogeneous imaging arrays. The control ultra-fine pitch (<10 mum) bumps count flip-chip bonding represents challenge on roadmap next generation devices (Kozlowski). This paper describes compares in details two new flip- technologies that can address challenges at 10 mum node: modified reflow soldering thermocompression "tip buried box" (TB2) insertion technology....

10.1109/ectc.2008.4549949 article EN 2008-05-01

We developed an innovative type of varifocal liquid lens actuated by electrostatic parallel plates. The 3mm diameter is made a polymer membrane that encapsulates high permittivity in cavity on top glass wafer. Annular electrodes situated below the and wafer form plates actuator. Applying voltage between reduces gap pushes towards center changing curvature membrane. Compared to previous lenses, significant outline improvement (<6×6×0.7 mm) supply reduction (<25 V ) demonstrated. Wave front...

10.1016/j.proeng.2010.09.139 article EN Procedia Engineering 2010-01-01

Devices for consumers like camera phones are essentially driven by the cost and performances. In that scope, several new key technologies requested to achieve a complete active waferlevel (with autofocus or zoom). A low vias interconnection has be developed conductive polymer is an attractive solution overcome this challenge. paper we describe technology fill insulated perform with screen printing equipment. first part, process flow compatible integration presented make metal routing. Then,...

10.1109/ectc.2011.5898742 article EN 2011-05-01

In this paper, CEA, LETI latest developments on thin film packaging technology are presented. Outgassing from materials used in TFP and MEMS devices become key parameters to decrease the pressure inside package improve reliability. a first part, some outgassing of typical Thin Film Packaging (TFP) measured under different time/temperature processes. Thanks these characterizations, an optimized baking process term time thermal budget can be defined. By minimizing outgassing, deposited by PVD...

10.1109/ectc.2012.6248812 article EN 2012-05-01

To overpass the bandwidth and latency limitations of electrical links, next breakthrough in high performance computing integration will eventually come through photonic technology Optical Network-on-Chip (ONoC). This work introduces a global architecture an ONoC reports detail fabrication on 200 mm Leti's platform Si interposer SOI wafers. Active circuit operating at 1310 nm wavelength, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML"...

10.1109/ectc51909.2023.00009 article EN 2023-05-01

Thin Film Packaging (TFP) is a cost effective packaging for MEMS, thanks to the wafer level process, silicon area saving, and compatibility with CMOS facilities. One of most important steps in this process sealing cap release holes after etching sacrificial layer. Standard processes are not well suited MEMS that require very controlled clean atmosphere's cavity or relatively high pressure like RF switches accelerometers. Such devices have operate at certain fulfill specifications sensitive...

10.1109/ectc.2015.7159769 article EN 2015-05-01

In this work, innovative solutions for the full manufacturing of a camera module at wafer scale (the level camera) are presented and discussed. order to replace glass carrier currently used in image sensors connected with TSV (Through Silicon Via), three different integration schemes (temporary bonding, cavities etched first last) proposed introduction silicon structured opened over sensor pixel area. Excellent electrical results demonstrated advantages limitations each scheme second part...

10.1109/ectc.2012.6249009 article EN 2012-05-01

MEMS Wafer Level Packaging is required for mass production of devices: wafer to bonding usually the current solution, however thin film encapsulation becomes a promising alternative method [1]. Nevertheless, major challenges should be overcome develop encapsulation, namely development cap strong enough withstand high mold pressures. Consequently, design tools are successfully [2–4]. For that, finite element models (FEM) commonly used, and this article proposes generic methodology based on an...

10.4071/2013dpc-tp35 article EN Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) 2013-01-01

Most of the time, MEMS devices require hermetic encapsulation for protection against atmosphere, moisture, particles and standard back-end manufacturing technologies. In last few years, Wafer Level Packaging (WLP) is moving toward developments on Thin Film (TFP) in order to save footprint, reduce chip thickness packaging costs. specific case high-vacuum (gyro, compass), long term pressure stability required. As final performances these kinds are strongly dependent working pressure, using TFP...

10.4071/2012dpc-tha31 article EN Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) 2012-01-01
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