A5091246814- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and interfaces
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Nanowire Synthesis and Applications
- 3D IC and TSV technologies
- Electronic and Structural Properties of Oxides
- Thin-Film Transistor Technologies
- Silicon and Solar Cell Technologies
- Organic Electronics and Photovoltaics
- Conducting polymers and applications
- Advancements in Photolithography Techniques
- GaN-based semiconductor devices and materials
- Organic Light-Emitting Diodes Research
- Semiconductor Quantum Structures and Devices
- Advanced Surface Polishing Techniques
- Surface and Thin Film Phenomena
- Radio Frequency Integrated Circuit Design
- Copper Interconnects and Reliability
- Molecular Junctions and Nanostructures
- Block Copolymer Self-Assembly
- Phase-change materials and chalcogenides
- Advanced Memory and Neural Computing
- Semiconductor Lasers and Optical Devices
University College Cork
2011-2019
IBM Research - Zurich
2014-2017
IBM (United States)
2014-2015
National University of Ireland
2014
Tyndall National Institute
2009-2014
Tyndall Centre
2010
Laboratoire des Sciences du Numérique de Nantes
2007
Nantes Université
2004-2005
In this work, we present the results of an investigation into effectiveness varying ammonium sulphide (NH4)2S concentrations in passivation n-type and p-type In0.53Ga0.47As. Samples were degreased immersed aqueous solutions 22%, 10%, 5%, or 1% for 20 min at 295 K, immediately prior to atomic layer deposition Al2O3. Multi-frequency capacitance-voltage (C-V) on capacitor structures indicate that lowest frequency dispersion over bias range examined occurs devices treated with 10%(NH4)2S...
We report on the first demonstration of CMOS-compatible integration high-quality InGaAs insulator (InGaAs-OI) Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based selective epitaxy, only requires use standard large-area silicon and typical CMOS processes. It enables fabrication InGaAs-OI starting from both bulk SOI wafers. The epitaxial structures are characterized very low defectivity, can fulfill requirements ultra-thin-body fins-based...
Extending the resolution and spatial proximity of lithographic patterning below critical dimensions 20 nm remains a key challenge with very-large-scale integration, especially if persistent scaling silicon electronic devices is sustained. One approach, which relies upon directed self-assembly block copolymers by chemical-epitaxy, capable achieving high density 1 : approaching 5 nm. Herein, we outline an integration-favourable strategy for fabricating areal arrays aligned nanowires PS-b-PMMA...
Block copolymer thin films require selective elimination of one their constituent blocks to access potential as lithographic nanopatterns. This paper demonstrates an on-substrate TEM-based approach for establishing the removal poly(methyl methyacrylate) from vertically oriented lamellar polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) and subsequent transfer underlying silicon by reactive ion etching. The ex situ microscopy technique presents insight into PMMA, etch end point, PS...
We investigated the effect of forming gas (5% H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /95% N ) annealing on surface-channel In xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As MOSFETs with atomic-layer-deposited Al O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> as gate dielectric. found that a anneal (FGA) at 300°C for 30 min was efficient removing or...
In this paper, we present a review of experimental results examining charged defect components in the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /In xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As metal-oxide-semiconductor (MOS) system. For analysis fixed oxide charge and interface state density, an approach is...
We report CMOS-compatible n-channel InGaAson-insulator FinFETs obtained using a replacement metal gate fabrication flow. The fabricated devices feature 12-nm-thick SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> spacers, scaled high-k/metal (capacitance equivalent thickness of ~1.5 nm), raised source and drain doped to ~6 × 10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> /cm...
We demonstrate, for the first time, scaled hybrid inverters built in a 3D Monolithic (3DM) CMOS process featuring short-channel replacement metal gate (RMG) InGaAs-OI wide-fin/planar nFET top layer and SiGe-OI fin pFET bottom layer. achieve state-of-the-art device integration, using raised source drain (RSD) on both levels silicide pFETs. Bottom pFETs are down to sub-20 nm length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) (GF)...
We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight viability our approach VLSI integration at advanced nodes. Short channel (RMG) and Gate-first (GF) FETs are reported time using InGaAs-OI wafers with 120nm contact-to-contact pitch. Record I <sub...
In this paper, state-of-the-art laser thermal annealing is used to form germanide contacts on n-doped Ge and systematically compared with results generated by conventional rapid annealing. Surface topography, interface quality, crystal structure, material stoichiometry are explored for both techniques. For electrical characterization, specific contact resistivity stability extracted. It shown that can produce a uniform remarkably smooth substrate two three orders of magnitude lower than the...
We provide the first report of structural and electrical properties TiN/ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ti/Al metal-insulator-metal capacitor structures, where ZrO thin film (7-8 nm) is deposited by ALD using new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance-voltage ( <i xmlns:xlink="http://www.w3.org/1999/xlink">C</i> -...
Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing high mobility lower processing temperatures, InGaAs is well-suited be used as top layer channel material in 3D along with Si/Si(Ge) FETs. A review of recent progress develop InGaAs-on-Si(Ge) Monolithic technology presented here.
The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) their surfaces using hydrogen silsesquioxane (HSQ) resist. HSQ offers highest resolution of all commercially available EBL resists. However, aqueous developers such as NaOH tetramethylammonium hydroxide have far prevented fabrication structures via direct application Bi2Se3, due solubility components respective oxides in these strong...
We report the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy standard front end line (FEOL) processes. This novel scalable integration scheme enables nFET fabrication in close proximity to SiGe pFETs (down 25 nm spacing), resulting 6T-SRAM having a minimum cell size below 0.45 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . can be combined any bulk Si or...
In this paper, the contact resistivity of NiGe on n-doped Ge is extracted. Although phosphorus slowest n-type dopant in terms diffusion Ge, corresponding data for are sparse. Contact dependence implant dose will be determined, as well a comparison phosphorus- and arsenic-doped layers. The impact high resistance evaluated future technology metal-oxide-semiconductor germanium devices.
The authors report on the structural and electrical properties of TiN/Al2O3/TiN metal–insulator–metal (MIM) capacitor structures in submicron three-dimensional (3D) trench geometries with an aspect ratio ∼30. A simplified process route was employed where three layers for MIM stack were deposited using atomic layer deposition (ALD) a single run at temperature 250 °C. TiN top bottom electrodes via plasma-enhanced ALD tetrakis(dimethylamino)titanium precursor. 3D devices yielded capacitance...
A Cl2/CH4/H2 inductively coupled plasma process without additional heating or wafer bonding is developed for the InP/InGaAsP material system. Vertical and smooth sidewalls can be observed in scanning electron microscope images. The main factors of etch rate, selectivity, sidewall roughness are analyzed relative to gas concentration a full factorial design experimental procedure. Under optimized conditions, an depth more than 3 μm with vertical obtained. strong indication passivation effect CH4