A5078467758- Cryptographic Implementations and Security
- Physical Unclonable Functions (PUFs) and Hardware Security
- Chaos-based Image/Signal Encryption
- Coding theory and cryptography
- Cryptography and Residue Arithmetic
- Cryptography and Data Security
- Advanced Malware Detection Techniques
- Security and Verification in Computing
- Quantum Computing Algorithms and Architecture
- Electrostatic Discharge in Electronics
- Network Packet Processing and Optimization
- Advancements in Semiconductor Devices and Circuit Design
- Quantum-Dot Cellular Automata
- Advanced Memory and Neural Computing
- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and devices
- Smart Grid Security and Resilience
- Software-Defined Networks and 5G
- Mobile Agent-Based Network Management
- Parallel Computing and Optimization Techniques
- Access Control and Trust
- Network Security and Intrusion Detection
- Multimedia Communication and Technology
- Network Time Synchronization Technologies
Nvidia (United States)
2025
Intel (United States)
2013-2023
CSIR National Physical Laboratory of India
2023
Academy of Scientific and Innovative Research
2023
Stony Brook University
2017
Indian Institute of Technology Kharagpur
2007-2016
KU Leuven
2012-2013
iMinds
2013
This article, for the first time, demonstrates Cross-device Deep Learning Side-Channel Attack (X-DeepSCA), achieving an accuracy of > 99.9%, even in presence significantly higher inter-device variations compared to inter-key variations. Augmenting traces captured from multiple devices training and with proper choice hyper-parameters, proposed 256-class Neural Network (DNN) learns accurately power side-channel leakage AES-128 target encryption engine, N-trace (N ≤ 10) X-DeepSCA attack breaks...
Computationally-secure cryptographic algorithms implemented on a physical platform leak significant "side-channel" information through their power supplies. Correlational attack is an efficient side-channel (SCA) technique, which analyzes the statistical correlation between estimated and measured supply current traces to extract secret key. The existing SCA countermeasures are mainly based reducing SNR of leaked information, balancing, or gate-level masking, each introduces power, area...
Power side-channel analysis (SCA) has been of immense interest to most embedded designers evaluate the physical security system. This work presents profiling-based cross-device power SCA attacks using deep learning techniques on 8-bit AVR microcontroller devices running AES-128. Firstly, we show practical issues that arise in these due significant device-to-device variations. Secondly, utilizing Principal Component Analysis (PCA) based pre-processing and multi-device training, a Multi-Layer...
Energy efficiency, performance and security of compact, self-powered, smart, secure connected motes at the edge IoT are critical for realizing intelligent, robust sustainable end-to-end cyberphysical systems that deliver compelling new capabilities based on big data analytics. Integrated ultra-low-power compute [1] wireless connectivity [2], neural-network-based inference accelerators [3], energy-efficient compact multi-sensing front end crypto engines, high density low leakage embedded...
The threat of side-channels is becoming increasingly prominent for resource-constrained internet-connected devices. While numerous power side-channel countermeasures have been proposed, a promising approach to protect the non-invasive electromagnetic attacks has relatively scarce. Today's availability high-resolution (EM) probes mandates need low-overhead solution EM analysis (SCA) attacks. This work, first time, performs white-box root-cause origin leakage from an integrated circuit....
This paper proposes a programmable GF( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> ) arithmetic unit for elliptic curve cryptography. The proposed can perform modular addition, subtraction, multiplication, inversion, and division. A suitable countermeasure against differential power analysis attack doubling is proposed. An scalar multiplication hardware subsequently designed the curves defined over using two cores of unit. It performs...
Mathematically secure cryptographic algorithms, when implemented on a physical substrate, leak critical "side-channel" information, leading to power and electromagnetic (EM) analysis attacks. Circuit-level protections involve switched capacitor, buck converter, or series low-dropout (LDO) regulator-based implementations, each of which suffers from significant power, area, performance tradeoffs has only achieved minimum traces disclosure (MTD) 10M till date. Utilizing an in-depth white-box...
Computationally-secure cryptographic algorithms when implemented on physical platforms leak critical signals correlated with the secret key in form of power consumption and electromagnetic (EM) emanations. This can be exploited by an adversary, leading to side-channel attacks (SCA) that recover key. Circuit-level on-chip countermeasures include a switched-capacitor current equalizer [1], charge-recovery logic [2], integrated voltage regulator (IVR) [3], all-digital low-dropout (LDO) [4],...
We propose design methodologies for building a compact, unified and programmable cryptoprocessor architecture that computes post-quantum key agreement digital signature. Synergies in the two types of cryptographic primitives are used to make compact. As case study, has been optimized targeting signature scheme 'CRYSTALS-Dilithium' encapsulation mechanism (KEM) 'Saber,' both finalists NIST's cryptography standardization project. The executes generations, encapsulations, decapsulations,...
Test compression is widely used for reducing test time and cost of a very large scale integration circuit. It also claimed to provide security against scan-based side-channel attacks. This paper pursues the legitimacy this claim presents scan attack vulnerabilities schemes in commercial electronic design automation tools. A publicly available advanced encryption standard structures provided by Synopsys, Cadence, Mentor Graphics testability tools are inserted into design. Experimental results...
With the advancement of technology in last few decades, leading to widespread availability miniaturized sensors and internet-connected things (IoT), security electronic devices has become a top priority. Side-channel attack (SCA) is one prominent methods break an encryption system by exploiting information leaked from physical devices. Correlational power (CPA) efficient side-channel technique, which analyses correlation between estimated measured supply current traces extract secret key....
Electromagnetic (EM) side-channel analysis (SCA) is a prominent tool to break mathematically-secure cryptographic engines, especially on resource-constrained devices.Presently, perform EM SCA an embedded device, the entire chip manually scanned and MTD (Minimum Traces Disclosure) performed at each point reveal secret key of encryption algorithm.However, automated end-to-end framework for leakage localization, trace acquisition, attack has been missing.This work proposes SCNIFFER: low-cost,...
This work presents a Cross-device Deep-Learning based Electromagnetic (EM-X-DL) side-channel analysis (SCA) on AES-128, in the presence of significantly lower signal-to-noise ratio (SNR) compared to previous works. Using novel algorithm intelligently select multiple training devices and proper choice hyperparameters, proposed 256-class deep neural network (DNN) can be trained efficiently utilizing pre-processing techniques like PCA, LDA, FFT measurements from target encryption engine running...
Mathematically secure cryptographic algorithms leak side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical sidechannel analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include current equalizer [1], series LDO [2], IVR [3], enhancing protection up 10M traces. Recently, domain signature attenuation [4] randomized NL-LDO cascaded with arithmetic [5] achieved >1B minimum traces disclosure (MTD) a single two...
Recently, a memory safety concept called Cryptographic Capability Computing (C3) has been proposed. C3 is the first mechanism that works without requiring extra storage for metadata and hence, potential to significantly enhance security of modern IT-systems at rather low cost. To achieve this, heavily relies on ultra-low-latency cryptographic primitives. However, most crucial primitive required by demands uncommon dimensions. partially encrypt 64-bit pointers, 24-bit tweakable block cipher...
Mathematically secure cryptographic algorithms leak meaningful side-channel information in the form of correlated power and electromagnetic (EM) signals, leading to physical analysis (SCA) attacks. Circuit-level countermeasures against power/EM SCA include a current equalizer, IVR, non-linear LDOs, enhancing protection up 10M traces, current-domain signature attenuation (CDSA), randomized NL-LDO cascaded with arithmetic achieved >1B. This work embraces concept analog CDSA but makes it easily...
This paper describes the systematic design methods of an embedded co-processor for a post quantum secure McEliece cryptosystem. A hardware/software co-design has been targeted realization in practice on low-cost platforms. Design optimizations take place when choosing system parameters, algorithm transformations, architecture choices, and arithmetic primitives. The final consists 8-bit PicoBlaze softcore flexibility several parallel acceleration units throughput optimization. prototype is...
Models and tools developed by the semiconductor community have matured over decades of use. As a result, hardware simulations can yield highly accurate easily automated pre-silicon estimates for e.g. timing area figures. In this work we design, implement, evaluate CASCADE, framework that combines largely full-stack standard-cell design flow with state art techniques side channel analysis. We show how it be used to efficiently leakage prior chip manufacturing. Moreover, is independent...
BIKE is a Key Encapsulation Mechanism selected as an alternate candidate in NIST’s PQC standardization process, which performance plays significant role the third round. This paper presents FPGA implementations of with best area-time reported literature. We optimize two key arithmetic operations, are sparse polynomial multiplication and inversion. Our multiplier achieves time-constancy for polynomials indefinite Hamming weight used BIKE’s encapsulation. The inversion based on extended...