Compared to the well understood macro networks, networks-on-chip introduce novel design challenges. The characteristics of system data flows and knowledge required wire lengths can be exploited optimize for speed power consumption. A component library flexible construction interconnection architectures is being developed at Tampere University Technology enable creation application development platforms. overall flow these platforms reviewed in this paper. Network-on-chip topology...

The issues of applying the code-division multiple access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A network-on-chip (NoC) that applies CDMA is realized register-transfer level (RTL) using VHDL. NoC supports globally-asynchronous locally-synchronous (GALS) scheme by both synchronous and asynchronous designs. In a NoC, which point-to-point connection scheme, e.g., ring topology data transfer latency varies largely if packets transferred...

Software Defined Radio (SDR) is an innovative approach which becoming a more and promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities industries to support SDR applications. This article presents overview current platforms analyzes related architectural choices, issues SDR, as well potential trends.

We observed several inefficiencies arising from the utilization of a global network to interconnect local bus clusters in our previous work. The observations were made with applications running on an FPGA prototype multimedia processing platform. presented network-on-chip concept has been designed eliminate these inefficiencies. This hierarchically heterogeneous architecture provides increased bandwidth inside by switches that replace shared buses. Features include priority-based low-latency...

This paper presents an accelerator-rich system-on-chip (SoC) architecture integrating many heterogeneous Coarse Grain Reconfigurable Arrays (CGRA) connected through a Network-on-Chip (NoC). The is designed to maximize the reconfigurable processing capacity for execution of massively parallel algorithms. central node NoC contains Reduced Instruction Set Computer (RISC) core that manages distribution computing functions and data within SoC while other nodes contain CGRAs application-specific...

An asynchronous FIFO which avoids data movement in a micropipeline is presented and it has been implemented as gate-level netlist. The model constructed by commonly used hardware-description language synthesized using the conventional EDA tools methods for synchronous design. purpose of this work to construct reusable design suits flow.

This paper presents a flexible timing synchronization scheme implemented on an Altera Stratix-V Field Programmable Gate Array (FPGA) device. The core content of the synchronizer is based reconfigurable Finite Impulse Response (FIR) filter which performs as multicorrelator demand. In concept flexibility, able to reconfigure its FIR block with Partial Reconfiguration (PR) feature, while rest design operating. Different architectures have been evaluated for design, including...

In this paper, we describe the design of a configurable Memory Management Unit (MMU) and its prototype implementation on Field Programmable Gate Array (FPGA). We present analytical results scaling size second level software-managed Unified Translation Lookaside Buffer (UTLB) in terms effect overall hit rate. Three design-time configurations with 16, 32, 64 entries were used for study. Critical path analysis logical running Altera Stratix-V FPGA is presented together description optimization...

A switching interconnection architecture with programmable priorities is described. The switch has been designed to replace shared buses in order increase bandwidth the local clusters of large systems-on-chip. design features guaranteed service for highest priority input port and best effort rest. Suitable standard cell fabrics are discussed their implementations compared. memory space conserving programming model presented together a low latency arbiter

An FPGA prototype of a four-node globally-asynchronous locally-synchronous network-on-chip is described. The network for global communication operates asynchronously at the link level and synchronously within node. Two C-element control pipelines constitute logic asynchronous part. arbiter realizations on using standard synchronous design tools are presented

In recent past, we scaled a 4 × 8 processing element (PE) template-based Coarse-Grain Reconfigurable Array (CGRA) to 4×4, 4×16 and 4×32 PE CGRA generated matrix-vector multiplication (MVM) accelerators from each one of them. Furthermore, on the accelerators, MVM kernels order N = 4; 8; 16; 32 were mapped. this paper, have estimated power energy consumption by generating postfit gate-level netlist accelerator for Field Programmable Gate as target platform. Based our measurements, studied...

A network node for Proteo network-on-chip (NoC) has been developed in order to support globally-asynchronous locally-synchronous (GALS) communication an on-chip system. The presented this paper was implemented as a synthesizable intellectual property (IP) block register-transfer level (RTL) using VHDL. proposed design applies both asynchronous and synchronous circuits make the globally data transfer rate between nodes independent of local clocks.

In recent past, we developed 4×8 and 4×16 processing element (PE) template-based Coarse-Grain Reconfigurable Arrays (CGRAs) mapped different length type of Fast Fourier Transform (FFT) algorithms on them. this paper, have considered radix-4 radix-(2, 4) FFT accelerators which were generated from 4 × 8 16 PE CGRA templates respectively. We estimated their power energy consumption while accelerator was 64 1024 points 128 algorithms. The by timing simulation postfit gate-level netlist both the...

In this paper, we have scaled-up a Coarse-Grain Reconfigurable Array (CGRA) in specific widths to evaluate matrix-vector multiplication and radix-4 64-point Fast Fourier Transform (FFT) algorithms. The evaluation of different CGRAs is based on complexity application mapping, performance area utilization. Reducing the product development time achieving higher reliability has always been need industry system integrators. low-level designers developers with minimum resources. Based our...