Software Defined Radio (SDR) is an innovative approach which becoming a more and promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities industries to support SDR applications. This article presents overview current platforms analyzes related architectural choices, issues SDR, as well potential trends.

Advanced coding schemes such as parallel concatenated zigzag (PCZZ) and LDPC codes are shown to provide performance close turbo codes. In this paper we propose PCZZ structured for an MB-OFDM UWB system with 16-QAM modulation aiming at increasing the data rate of current up 1 Gbps. We evaluate in a system. particular, it is that 3-4 dB gain packet error compared convolutional also address link budget achievable ranges different rates. The proposed may be considered potential channel scheme...

Applying design principles and methodologies constituted in the software domain being adapted to complete execution environment provides new perspectives for future multi-radio computers. In order share underlying hardware resources efficiently, overall system architecture related programming model has support dynamic behavior extensive changes configuration during run-time. The requirements such a computer are demanding, as there will be various radio access stacks with inhomogeneous...

Sine is one of the fundamental mathematic functions which are widely used in a number application fields. In particular, signal processing and telecommunications need to calculate sine cosine numerical values for several different purposes. One challenges affected implementation calculation digital (DSP) has been method it by means rational functions, would allow computer system. possibility exploit Taylor polynomials, even though their main drawback consists relatively high grade (thus...

Parallel implementations of Turbo decoding has been studied extensively. Traditionally, the number parallel sub-decoders is limited to maintain acceptable code block error rate performance loss caused by edge effect division. In addition, require synchronization exchange information in iterative process. this paper, we propose loosening between achieve higher utilization processor resources. Our method allows high degree a single providing scalable software-based implementation. The proposed...

Turbo coding is commonly used in the current wireless standards such as 3G and 4G. However, due to high computational requirements, its software-defined implementation challenging. This paper proposes a static multi-issue exposed datapath processor design tailored for turbo decoding. In order utilize parallel efficiently without resorting low level assembly programming, decoder implemented using OpenCL, programming standard heterogeneous devices. The proposed includes only small set of...

A standard-throughput-approaching LDPC decoder has been implemented on a mid-range GPU in this paper. Turbo-Decoding Message-Passing algorithm is applied to achieve high throughput. Different from traditional host managed multi-streams hide host-device transfer delay, we use kernel maintained data scheme implicit between memory and device shared memory, which eliminates an intermediate stage of global memory. Data type optimization, accessing low complexity Soft-In Soft-Out are also used...

This paper proposes a single instruction multiple data (SIMD) processor, which is programmed with high-level OpenCL language. The low-power processor customized for executing multiple-input-multiple-output (MIMO) detection algorithms at high performance while consuming very little power making it suitable software-defined radio (SDR) applications. novel combination of SIMD operations on transport multicore datapath allows saving both the execution front end and back end, leading to good...

The SRAM memories used for embedded micro-processor devices consume a large portion of the system's power. power dissipation instruction memory can be limited by using code compression methods, which may require use variable length formats in processor. power-efficient design fetch and decode is challenging static multiple-issue processors, aim low consumption on platforms. saved easily lost inefficient processor design. We propose an implementation template -based two alternatives encoding...

In this paper, we propose a joint reduced-state sequence estimator (JRSSE) for multiple input output (MIMO) system. The proposed JRSSE incorporates the set-partitioning principle to obtain trellis and is space-time extension of RSSE earlier single input, (SISO) temporal equalization problem. We show that two elements are essential in achieving desired complexity performance tradeoff algorithm: proper multi-symbol set-partition an efficient structure effectively decouples spatial processing....

The downlink link-level performance assessment, through simulations, is given in this paper for an LTE (and LTE-A) UE receiver, interference-limited scenarios, and the presence of RF impairments both synchronous asynchronous networks. data channel (PDSCH) receiver based on linear MMSE filter adapted accordingly to interference environment covariance estimation its inclusion into calculation. A suboptimum MMSE-based also derived transmit-diversity scheme interference, showing excellent...

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required wireless IoT nodes. Otherwise, by communication of raw sensor data will prohibit battery lifetime, backbone IoT. One option to achive this implement a variety machine learning algorithms on instead cloud. Shown here sub-milliwatt accelerator operating at Ultra-Low Voltage Minimum-Energy Point. The Transport Triggered Architecture (TTA) Application-Specific Instruction-Set Processor (ASIP) targeted for...

Power consumption in modern processor design is a key aspect. Optimizing the for power leads to direct savings battery energy case of mobile devices. At same time, many applications demand high computational performance. In large scale computing, low compute devices help thermal and reducing electricity bill. This paper presents study customized vector that was synthesized on 28 nm process technology. The has programmer exposed datapath based transport triggered architecture programming...

We analyze, by means of link and network simulations, the gain in capacity, throughput packet delay reduction achievable using an advanced dual antenna interference suppression receiver EGPRS terminals. is enhanced radio system GSM standard. focus on a small macrocellular environment with severe cochannel interference, which most capacity limited scenario. The results show significant gains from diversity.

ETSI DECT-2020 New Radio (NR) is a new flexible radio interface targeted to support broad range of wireless Internet Things (IoT) applications. Recent reports have shown that NR achieves good delay performance and it has been fulfill both massive machine-type communications (mMTC) ultra-reliable low latency (URLLC) requirements for 5th generation (5G) networks. A unique aspect as 5G technology an autonomous mesh network (WMN) protocol where the devices construct uphold independently without...

This paper presents some OpenCL implementations for Cholesky decomposition, a very popular algorithm used in linear algebra and signal processing applications. The represents interesting candidate implementation since it contains sequential parts besides parallel ones. Furthermore, one step involves just small amount of calculations. These characteristics pose challenges which call suitable techniques to overcome the limitations language. We propose several versions algorithm, then provide...