A5008010401- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Analog and Mixed-Signal Circuit Design
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Low-power high-performance VLSI design
- Optical Network Technologies
- Electromagnetic Compatibility and Noise Suppression
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Interconnection Networks and Systems
- CCD and CMOS Imaging Sensors
- Parallel Computing and Optimization Techniques
- Advanced DC-DC Converters
- Advanced MEMS and NEMS Technologies
- Advanced Data Storage Technologies
- Advanced Memory and Neural Computing
- Advanced Photonic Communication Systems
- 3D IC and TSV technologies
- Thin-Film Transistor Technologies
- Microwave Engineering and Waveguides
- Multilevel Inverters and Converters
- Real-Time Systems Scheduling
- Advanced Power Amplifier Design
Seoul National University
2016-2025
University of California, Davis
2020
University of Seoul
2020
Samsung (South Korea)
2014
Philips (Finland)
2002
New York University
1997
National Tsing Hua University
1992
Texas Instruments (United States)
1989-1990
University of California, Berkeley
1987-1990
Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic circuit. Power comparison with other circuits performed on an inverter chain and carry lookahead adder (CLA). ECRL CLA designed pipelined structure obtaining the same throughput conventional static CMOS CLA. Proposed shows four to six times power reduction practical loading operation frequency range. An inductor-based supply clock generation circuit proposed. Circuits are using 1.0-/spl mu/m technology...
With the increasing computational demands of neural networks, many hardware accelerators for networks have been proposed. Such existing network often focus on popular types such as convolutional (CNNs) and recurrent (RNNs); however, not much attention has paid to mechanisms, an emerging primitive that enables retrieve most relevant information from a knowledge-base, external memory, or past states. The mechanism is widely adopted by state-of-the-art computer vision, natural language...
This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL fully utilize the frequency range of voltage-controlled line. The proposed keeps same benefits DLLs such as good jitter performance clock generation. incorporates dynamic phase detectors triply controlled cells with cell-level duty-cycle correction capability generate equally spaced...
The design of clock generation circuitry being used as a part high-performance microprocessor chip set is described. A self-calibrating tapped delay line to generate four nonoverlapping phases system clock. charge-pump phase-locked loop (PLL) calibrates the per stage line. Using this technique, it possible obtain an accurate phase relationship between off-chip reference and internal signals. Experimental results show that required timing relations can be obtained with less than 2-ns skew for...
A charge pump that minimises the mismatch between charging and discharging currents keeps constant across a wide output voltage range is described. The improved current matching helps reduce static phase offset reference spur of charge-pump phase-locked loop (PLL) help control PLL dynamics precisely. proposed with dual compensation circuits demonstrates less than 3.2% pump-current variation 1.7% over ranging from 0.2 to 1.0 V in 0.13 µm CMOS process 1.2 supply.
A single-inductor boost light-emitting diode (LED) driver that can distribute equal dc currents to multiple channels of LEDs is presented. To ensure uniform brightness in display backlight units, the previous approaches used current regulation elements serially inserted individual LED channels, which incur power losses. Instead, proposed adopts a single-inductor-multiple-output converter topology, keeps channel an open-loop fashion by connecting current-delivering inductor each for period...
This paper describes a high-speed CMOS adaptive cable equalizer using an enhanced low-frequency gain control method. The additional loop enables the use of open-loop equalizing filter, which alleviates speed bottleneck conventional adaptation In addition, combined and high-frequency boosting improves accuracy while supporting operation. filter incorporates merged-path topology offers infinite input impedance, are suitable for higher frequency operation cascaded design. controls its...
This paper describes an I/O scheme for use in a high-speed bus which eliminates setup and hold time requirements between clock data by using oversampling method. The circuit uses low jitter phase-locked loop (PLL) suppresses the effect of supply noise. Measured results show peak-to-peak 150 ps r.m.s. 15.7 on line. Two experimental chips with 4-pin interface have been fabricated 0.6 /spl mu/m CMOS technology, exhibits bandwidth 960 Mb/s per pin.
This paper addresses issues with time synchronization using the IEEE 1588-2008 for distributed measurement and control systems. A practical implementation of transparent clock is presented overall system architecture detailed operation each building block. To verify submicrosecond accuracy implemented devices, an experimental setup that was analogous to a has been built. Measured results from experiment show error limited below 30 ns nodes were connected by three switches. It remarkable are...
We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated PIC(off-chip) optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the 1 mm-phase-shifter modulator in demonstrated extinction ratio (ER) 10.5dB...
This paper describes a capacitive touch-screen panel (TSP) readout IC that provides reconfigurable SNR and frame rate with high noise immunity touch sensitivity. The mitigates severe interference lock-in sensing architecture. In addition, band-pass filtering effect by the TSP charge amplifier further improves immunity. A differential scheme is employed to enhance sensitivity reject common-mode noise. column-parallel incremental ΣΔ ADC adopted provide resolution rate. Furthermore, multiple...
This paper presents an ac-dc LED driver that consists of two-parallel inverted buck converters. To buffer the twice-line-frequency energy, one converter (also known as a floating converter) conveys energy to storage capacitor, simultaneously performing power factor correction. The other regulates current maintain constant brightness in LEDs for reducing light flicker low-risk levels. proposed architecture reduces voltage stress and size enabling use film capacitor instead electrolytic...
This paper describes the design of a 10 GHz phase-locked loop (PLL) for 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide four-phase, clock quarter-rate TX. Several analyses and verification techniques, ranging from clocking architectures TX oscillation failures in oscillator, are addressed this paper. tri-state-inverter-based frequency-divider an AC-coupled clock-buffer high-speed operations with minimal power area overheads. The proposed PLL fabricated 65...
In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign-sign least-mean-squares (SSLMS) algorithm applied to adaptation for not only decision feedback equalizer (DFE) but also continuous-time linear (CTLE) unify the methods. This approach facilitates concurrent that results in short time and reduces extra hardware power consumption. An average value of fourth- fifth-post-cursors used as an indicator CTLE adaptation, validity...
A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is in a 0.35-/spl mu/m technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, improved architecture dual-path loop filter makes it possible implement large time constant on chip. With current-feedback bias coarse tuning, voltage-controlled oscillator (VCO) enables power low gain VCO. Power dissipation 60 mW with 3.0-V supply. provides 10-kHz channel...
This paper describes the design and implementation of an all-digital clock data recovery circuit (ADCDR) for multigigabit/s operation. The proposed digitally-controlled oscillator (DCO) incorporating a supply-controlled ring with resistor (DCR) generates wide-frequency-range multiphase clocks fine resolution. With adaptive proportional gain controller (APGC) which continuously adjusts gain, ADCDR recovers low-jitter tracks large input jitter rapidly, resulting in enhanced performance. A...
An all-digital phase-locked loop with a bang-bang phase-frequency detector (BBPFD) that tracks the optimum gain for minimum jitter is proposed. The autocorrelation of output BBPFD indicates whether PLL operates in nonlinear regime or random noise regime. adaptive controller continuously evaluates and adjusts to make zero. digital filter at higher than reference clock frequency reduce latency mitigate resolution digitally controlled oscillator. prototype chip has been fabricated 65-nm CMOS...
This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in 65 nm CMOS process. The consists of front-end half-rate bang-bang circuit. achieves low power consumption by using inverter-based amplifiers realizes sufficient bandwidth applying several extension techniques. In addition, order minimize additional jitter at the front-end, not only magnitude but also group-delay responses are considered. AD-CDR employs LC quadrature...
The sneak current through the neighboring cells interrupts reading of a selected cell in high‐resistance state crossbar resistance switching random access memory (RRAM). As mainly originates from parallel component to cell, write operation, which requires sufficiently high voltage delivered has been regarded have little relevance issue. In this work, it is revealed that an additional drop on wire resistances word and bit lines causes increase for operation (programming/erasing), whose degree...
This paper presents a touch sensing analog front end (AFE) for capacitive touch-screen integrated into an ultra-thin display. Reduced distance between the screen and display causes large coupling, resulting in increased parasitic capacitance reduced sensitivity. Display noise interference is worse due to coupling capacitance. Hence, it challenge design AFE capable of accurate energy efficient input panel. An adiabatic multi-driving method based on charge recycling proposed provide...
This paper presents a fully synthesizable successive-approximation-register (SAR) analog-to-digital converter (ADC) for on-chip distributed waveform monitoring in low-power system-on-chip (SoC). All blocks the proposed ADC are designed using only standard digital cells, enabling an auto-generation based on regular design tools. Therefore, provides enhanced portability and reusability which facilitate integration into various functional requiring testing diagnosis. To implement SAR ADC,...
This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud data communication. The is robust and low-cost solution to high rate requirements. A central charge pump PLL for generating multiphase clocks oversampling shared by several channels. Fully communication realized in the bidirectional bridge separating incoming from mixed signal on cable end. digital accomplishes process-independent recovery using low-ratio oversampling, majority voting, parallel scheme. Mostly, approach...
This article addresses issues with designing a blind oversampling clock and data recovery unit (CDR) that meets jitter tolerance specifications. Asymptotic limits on are derived assuming ideal phase detection based priori statistics of the received signal, proving coarse timing resolution CDR relies algorithm makes good estimates signal's finite number discrete samples at reasonable hardware costs. The statistical simulation methodology outlined here enables quick verification bit error rate...
This paper describes a clock/data recovery circuit (CDR) incorporating variable-interval 3/spl times/-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place data-sampling clock exactly at center of data eye, responding shape and magnitude jitter. A sampler with pair input-holding switches enables high-speed sampling reduced dynamic offset voltage. From linearized model phase detector, loop dynamics are analyzed. Integrated in...
This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers DC-offset cancellation scheme. The scheme combined multiphase sampling fractional-N prescaler alleviates the problems of receiver. Digital gain control is merged into baseband filters variable-gain amplifiers to optimize linearity system, reduce noise, improve sensitivity. Variable-gain loop eliminate in each stage. chip implemented 0.35-μm CMOS...