A5064808352- Advancements in PLL and VCO Technologies
- Photonic and Optical Devices
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Optical Network Technologies
- Semiconductor Lasers and Optical Devices
- Advancements in Semiconductor Devices and Circuit Design
- Interconnection Networks and Systems
- Semiconductor materials and devices
- Advanced Electrical Measurement Techniques
- Ferroelectric and Negative Capacitance Devices
- Advanced Photonic Communication Systems
- Low-power high-performance VLSI design
- Electromagnetic Compatibility and Noise Suppression
- Integrated Circuits and Semiconductor Failure Analysis
- Mechanical and Optical Resonators
University of Illinois Urbana-Champaign
2012-2024
University of Illinois System
2023-2024
Seoul National University
2011-2013
We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated PIC(off-chip) optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the 1 mm-phase-shifter modulator in demonstrated extinction ratio (ER) 10.5dB...
In this paper, first, we describe an impedance-matched bi-directional multi-drop (IMBM) DQ bus that can handle up to 4 slots, 8 drops at a data-rate of 4.8Gb/s. the case SSTL bus, series resistor Z0/2 suppress ringing and attenuate reflections within chan nel. But, is still not entirely free from among slots because reflection coefficient stub junctions -1/4. However, IMBM propose makes coef ficient 0 as be seen equations. Therefore, generates no signal each stub. Moreover, send write...
Monolithic RC oscillators are increasingly becoming the preferred clock source in many applications, which typically have used bulky crystal or MEMS oscillators. Using novel methods to compensate for frequency inaccuracy caused by temperature coefficient (TC) of resistors reference networks, prior works achieved excellent short-term stability [1], [2]. While this level performance undoubtedly makes a desirable option even applications requiring medium-to-high sources, they cannot be deployed...
A low-jitter multi-phase clock generator is pivotal in high-speed serial link transceivers. With data rates surpassing 100Gb/s, incorporating sub-rate operations becomes essential to overcome inherent bandwidth constraints. This, turn, demands the generation of multiple phases. However, difficulty lies producing these signals with minimal jitter, particularly at high frequencies (>10 GHz). Contemporary generators integrated jitter below $100\mathrm{fs}_{\mathrm{rms}}$ primarily utilize LC...
On-chip RC-based frequency references are increasingly being used to generate device clocks. They consume lower power, occupy a small area, and do not require costly off-chip components. However, poor accuracy resulting from their non-linear temperature sensitivity has limited usage systems that can tolerate large inaccuracy (~1%). Several efforts underway reduce the extend use real-time clock sources mandate more stringent (±250ppm). Among reported schemes, those based on 2-point digital...
The increasing intra-datacenter traffic is pushing the demand for ultra-high-speed optical interconnect that maximizes both power efficiency and data rate per wavelength. Intensity modulation-direct detection (IM-DD) links are used in these short-reach applications because of their simplicity low consumption; however, rates becoming exceedingly difficult due to technology- packaging-imposed constraints. Coherent links, traditionally long-reach applications, gaining traction as an alternative...
This paper describes the design and performance of a 10-Gb/s optical receiver front-end fabricated in 0.13-μm CMOS technology. To realize wide bandwidth transimpedance amplifier (TIA) that has large input parasitic capacitance, an area-efficient stacked spiral transformer is implemented. By using capacitance multiplication technique, baseline wander resulting from current offset cancellation minimized. The TIA achieves gain 58.5dBΩ, area 0.02mm <sup...
In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for memory controller that supports bus. Reflective ISI is eliminated at each stub of the IMBM bus by resistive unidirectional impedance matching. A prototype designed and fabricated in 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS...
A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic used speed up the locking of FLL, truncation error cancellation (TEC) performed in FDIVs reduce delta-sigma-induced jitter. prototype fabricated 65-nm CMOS process generates clocks range 1.5–100 MHz with resolution 24-kHz, 140-ps...
This article presents a temperature-and agingcompensated RC oscillator (TACO) in which the long-term drift of main is compensated by periodically locking its frequency to that less-aged reference oscillator.To improve stability TACO, it employs techniques, such as use higher activation energy (E ) resistors, switched dual branches mitigate stress from dc-current-induced electromigration (EM), and duty cycling slow down aging rate oscillator.Using proposed prototype 100-MHz fabricated 65-nm...
The demand for portable electronic devices with a small form factor and extended battery life is ever increasing. Timing circuits impose several critical impediments in meeting this demand. For example, low-power microcontroller units use multiple crystal oscillators (XOs) on-chip fractional-N phase-locked loops (PLLs) to generate the desired clocks, which significantly increase board space, power consumption. XOs PLLs cannot be turned ON OFF rapidly, so they also severely limit ability...
This article presents techniques to improve the frequency stability of RC oscillators by performing firstand second-order temperature compensation without needing resistors with opposite coefficients (TCs).Using proposed three-point digital trim, a prototype 100-MHz frequency-locked loop (FLL)-based oscillator fabricated in 65-nm CMOS process achieves an inaccuracy ±140 ppm over -40 • C 95 C, 83-ppm/V voltage sensitivity, 1.3-ppm Allan deviation floor, and 1-µW/MHz power efficiency.When only...