Two integrated high-speed gate drivers to enable high-frequency operation of synchronous rectifiers in high-voltage switching power converters are presented this paper. The first driver for a CMOS train consists capacitively coupled level shifter (CCLS) that offers negligible propagation delays and no static current consumption, requires only one off-chip capacitor high-side pMOS driving capability without any external floating supply. second low-power dynamically controlled (DCLS) with...

This paper presents an efficiency-enhanced low-profile zero-voltage-transition (ZVT) synchronous non-inverting buck-boost converter for 48-V tens-of-Watt output applications. By only using three auxiliary components shared between two switching nodes, zero-voltage (ZVS) of all four power switches and zero-current the switch are achieved in proposed to minimize loss. Compared with existing ZVT topologies, reduces required number components, thereby decreasing volume In addition, can be...

Bệnh viêm loét đại trực tràng chảy máu (VLDTTCM) là bệnh mạn tính, có thể ảnh hưởng đến chất lượng sống của nhân (BN). Mục tiêu nghiên cứu “Đánh giá theo thang điểm SF-12 và một số yếu tố liên quan”. Đối tượng phương pháp: mô tả cắt ngang trên 60 BN được dõi điều trị tại Trung tâm Tiêu hoá – Gan mật, viện Bạch Mai trong thời gian từ 01/2024 04/2024. Kết quả: SF-12, trung bình sức khoẻ (PCS) 35,5 ± 8,4, thần (MCS) 43,6 11,9 cuộc chung 48,9 22,2. Không sự khác biệt giữa PCS MCS với tuổi, giới,...

This paper presents a wide-range high-voltage (HV) isolated phase-shifted full-bridge dc-dc bus converter with eGaN power FETs driven by an integrated synchronous CMOS gate driver. The monolithic slope-sensing zero-voltage switching detector (SS-ZVSD) is developed to automatically provide adaptive deadtime control near-constant short turn-on delay for enabling ZVS of transistors during transitions under different input voltages and load currents. not only minimizes the loss reverse...

A C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on interconnecting nodes a ladder significantly deteriorate linearity restrict application. In this paper, pseudo structure proposed. It maintains advantages conventional ladders effectively compensates for effects by adjusting capacitor ratio in C-2/spl alpha/C ladder. As result, may be achieved standard CMOS technologies....

The impact of a deuterium (D2) sinter under two different annealing conditions, 450 °C/60 min and °C/90 min, was studied compared to the traditional forming gas (FG) sinter. Channel hot carrier (CHC) measurements indicated that while D2 for 60 improves lifetime devices by 10× over FG sinter, an additional increase in anneal time actually has negative on lifetime. DC current–voltage also showed samples sintered ambient were least prone degradation stress. Gated diode results no appreciable...

The growing development of industrial power supplies demands DC-DC converters that are increasingly efficient and reliable. Industrial bus operate from a front-end PFC could experience fluctuations 150V to 400V [1]. This requires isolated function over wide range the high-input condition. Zero-voltage switching (ZVS) with proper dead-time control is essential in these remove dominant loss for achieving better efficiency. Specifically, each FET should be controlled turn on right after its ZVS...

This paper presents an integrated reconfigurable high-voltage (HV) synchronous gate driver for driving eGaN FET and Si-MOSFET power switches that have different turn-on-voltage requirements. The proposed has a comparator-based dynamic dead-time controller to enable zero-voltage-switching operation of both high- low-side FETs with minimal body diode conduction loss. Thanks the HV level shifter, large transient current can be generated under high dV/dt at converter switching node reliability...

In modern hybrid electric vehicles, wide-input-range intermediate bus converters (IBCs) are essential in 48V power systems [1]. To increase the efficiency, e-mode GaN FETs have been adopted IBCs [2, 3], as they offer much smaller on-resistance and thus conduction loss than silicon FETs. However, even with FETs, hard-switching (HS) would still suffer from considerable turn-on V-I overlap dV/dt kickback at high input voltages, degrading light-load limiting switching frequency (f <sub...

A PWM or quasi-square-wave (QSW) zero-voltage-switching (ZVS) non-isolated boost converter using enhancement-mode GaN (eGaN) FETs is reported in this paper. The new topology requires small number of passive components, minimizes the switching loss under high-voltage high-frequency operations, and offers low-voltage stress across power transistors. transformer-based floating gate driver with 30 ns propagation delay 3 rising/falling time developed to enable high-speed high-side driving eGaN...

This paper presents techniques for high-voltage converters to achieve high power efficiency at switching frequency. A quasi-square-wave zero-voltage isolated three-level half-bridge architecture is proposed minimize the converter loss under high-frequency conditions. synchronous gate driver with dynamic dead-time control also developed ensure reliability of all eGaN FETs, automatically generate appropriate FETs ZVS minimal reverse bias behavior, and provide fast propagation delays operation....

This paper presents techniques for high-voltage isolated converters to achieve high power efficiency at switching frequencies. To minimize the converter loss, an quasi-square-wave zero-voltage three-level half-bridge architecture is adopted. An integrated synchronous gate driver proposed ensure reliability of all eGaN FETs and provide fast propagation delays high-frequency operation. Thanks auto-reconfigurability V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

This paper presents a high-frequency high-efficiency two-phase buck converter with quasi-square-wave (QSW) ZVS scheme for high-voltage automotive applications. A set of auxiliary inductor and capacitor is shared between sub-converters to realize all power FETs minimize switching loss under conditions. The proposed structure reduces the required current ripple in inductor, thereby reducing core at high frequency. sizes main output are also reduced due cancellation converter. With...

C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on interconnecting nodes ladder restrict linearity DAC. In this paper, a pseudo structure proposed. It compensates for effect by adjusting capacitor values in ladders according to an optimization algorithm with further adjustments possible via adaptive calibration method. Using technique, 3.3 V 9.2 mW 12-bit 1.4 MSPS successive...

This paper presents a fully-integrated high-voltage (HV) synchronous gate driver for driving power switches in zero-voltage switching (ZVS) converters. The proposed monitors the drain-source voltage of both high-side and low-side FETs determines proper dead time to turn on under ZVS conditions. Compared with traditional off-chip detection scheme which typically requires an additional transformer winding, design incorporates detector into monolithic minimize volume magnetics other external...

This article presents a dc–dc bus converter with new soft-switching scheme. Adaptive zero-voltage transition (AZVT) is proposed to enable ZVS turn-on of the power FET via ZVT auxiliary branch for removing switching loss converter. In AZVT, current discontinuous and its peak value controlled decrease load current. feature not only minimizes conduction but also significantly improves light-load efficiency addition, high-voltage flipped sensor (HVFCS) developed fast accurate inductor sensing...

A micro acoustic sensor with inclined fibers was proposed to improve its sensitivity. In order get the highest sensitivity within structure, relative positions of elements in should be exactly located; especially distance between and membrane optimum. packaging technology for this assemblage test is introduced. It based on a system composed three parts: adjusting, intensity collection data analysis. The adjusting part increases operating step 2μm. Meanwhile received power recorded by line...

In this paper, an 8/16× time amplifier (TA) using ring oscillator (ROSC) is presented. For a wide input range, register (TR) based on gated (GRO) proposed which has variable capacity and can realize the accumulation subtraction of time. Together with double multiplication phase detector (PD), TA implemented, achieves range more than ±200ps, programmable gain without any calibration. The error less ±4.5% in all modes under various process, voltage, temperature (PVT), while consuming 477uw...

In the space environment, precision of fibre optic gyroscopes (FOGs) degrades because radiation. Photonic components FOGs are affected by radiation, especially polarization-maintaining (PM) coil. relation to radiation environment characteristic, we have carried out a series experiments on PM coil with 60Co source at different dose rates. Based experimental results, formula between PM-fibre loss and rate is built, FOG obtained accordingly. The results strongly show that our owing attenuation...

This paper presents a synthesizable cyclic vernier time to digital converter (TDC) based on ring oscillators. All circuits are automatically placed and routed without any custom layout or design. The mismatch in the eliminated by proposed calibration circuit, which utilizes effect that amplified signal can be much larger than of wire parasitic, thus cancelling its own mismatch. designed circuit stops working during conversion save power consumption. To areas, counter is re-used period...

This paper presents various circuit techniques and design considerations for high-voltage integrated switching converters to enable their high-frequency operation, thereby minimizing the converter cost, weight volume. First, of realizing a low-power high-speed synchronous gate driver power FETs are explained in order allow operating MHz range with negligible efficiency degradation. The high-accuracy sense-FET based current sensor monitor peak inductor is also discussed. To demonstrate above...