In emerging Spiking Neural Network (SNN) based neuromorphic hardware design, energy efficiency and on-line learning are attractive advantages mainly contributed by bio-inspired local with nonlinear dynamics at the cost of associated complexity. This paper presents a novel SNN design employing fast COordinate Rotation DIgital Computer (CORDIC) algorithm to achieve spike timing–dependent plasticity (STDP) high efficiency. this study, system evaluation method CORDIC-based is proposed for...

Bio-inspired neuron models are the key building blocks of brain-like neural networks for brain-science exploration and neuromorphic engineering applications. The efficient hardware design bio-inspired is one challenges to implement networks, as balancing model accuracy, energy consumption cost very challenging. This paper proposes a high-accuracy energy-efficient Fast-Convergence COordinate Rotation DIgital Computer (FC-CORDIC) based Izhikevich design. For ensuring an error propagation...

Stateful logic through memristor is a promising technology to build Computing-in-Memory (CIM) systems. However, aging-induced degradation of memristors' threshold voltage imposes major challenge the reliability and guardbands estimation memristive CIM systems, especially Material Implication (IMPLY) based In this paper, novel in-situ aging-aware error monitoring scheme for memristor-based IMPLY proposed. The proposed can achieve faster detection speed higher accuracy than straightforward...

In order to alleviate the scale variation problem in object detection, many feature pyramid networks are developed. this paper, we rethink issues existing current methods and design a more effective module for fusion, called multiflow fusion (MF 3 M). We first construct gate modules multiple information flows MF M avoid redundancy enhance completeness accuracy of transfer between maps. Furtherore, reduce discrepancy classification regression modified deformable convolution which is termed...

This paper presents a security strategy for resisting physical attack utilizing data remanence in powered-off static random access memory (SRAM). Based on the mechanism of to remanence, intends erase cells once power supply is removed, which disturbs attackers trying steal right information. Novel on-chip secure circuits including and transistor are integrated into conventional SRAM realize operation. Implemented 0.25 μm Huahong-NEC CMOS technology, an exploiting proposed shows operation...

Simultaneous localization and mapping (SLAM) is the major solution for constructing or updating a map of an unknown environment while simultaneously keeping track mobile robot's location. Correlative Scan Matching (CSM) scan matching algorithm obtaining posterior distribution probability pose in SLAM. This paper combines non-linear optimization CSM into NLO-CSM (Non-linear Optimization CSM) reducing computation resources amount ensuring high calculation accuracy, it presents efficient...

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I–V transconductance characteristics MOSFET operating in region and enhancement pre-regulator gain negative feedback loop for core circuit. circuit, designed SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable about 1.701 μA much low temperature coefficient 2.5×10−4 μA/°C range −40 to 150 °C at 1.5 V voltage,...

Matrix multiplication is an essential mathematical calculation in a wide range applications of signal processing, computer graphics and intelligent robots. The autonomous robots involves various navigation algorithms (e.g. Extended Kalman Filter (EKF), reinforcement learning, A* artificial potential field, etc.) [1] –[4] deep neural network (DNN) Darknet YOLOv3), which all contain intensive matrix multiplications with different sizes shapes. emerging Intelligent Autonomous Mobile Robots...

An output-capacitorless low-dropout regulator (OCL-LDO), which is based on flipped-voltage-follower (FVF) using damping-factor-control (DFC) frequency compensation for SOC application, presented in this paper. The proposed LDO with 1.2V supply, 100mA load current was designed by SMIC 0.13um standard CMOS process. Simulation results have shown that the can be stable a capacitance ranging from 0 to 80pF. line regulation and are 3.3mV/V 62uV/mA, respectively, quiescent consumption only 27uA....

Efficient hardware design of biological neuron models is an essential issue in neuromorphic computation research. This paper presents a high-accuracy and energy-efficient Izhikevich neuron, which fast-convergence COordinate Rotation DIgital Computer (CORDIC) operating linear system proposed to calculate square function. A CORDIC error model also analyze the propagation study accuracy improvement design. Utilizing fast instead conventional CORDIC, redundant iterations associated are removed,...

A novel high-performance low density parity check codes (LDPC) decoder with small die size for IEEE802.16e criteria is presented in this paper. It utilizes the decoding technique called "Turbo Decoding Message Passing (TDMP)" and a new hardware architecture based on Ping-Pong operation. Under generic digital logic process of UMC, when working frequency 67MHz, paper has cell area 7.19mm2, layout 10.72mm2, maximum throughput 1.1Gbps. The simulation results show that under AWGN channel SNR 3dB,...

This paper presents a theoretical study on clock control strategy of four-phase Dickson charge pump for improving the power efficiency. Optimized signals attains better efficiency when compare conventional designs. Simulation results based 0.25 mum CMOS technology are presented to validate analysis.

Most information in an image is contained the edge. Sobel edge detection algorithm a classic method to realize of applications robot vision, including motion and object tracking. This paper proposes area-efficient energy-efficient detector design utilizing bit-width pruning, shift-add operation tuning techniques, reduce required area computation significantly with negligible loss, for mobile vision applications. As result, proposed can achieve lower hardware overhead higher energy...

This paper designed a low-noise high-gain tran simpedance amplifier with high dynamic range. The input stage of TIA uses an individual power supply to accommodate the level photodiode(PD). Then signal is transmitted subsequent circuit by shifting circuit. adopts DCrestore stabilize work points, and MOS working in linear region reduce effective realize Key noise components are optimized referred current noise. was validated 0.13 urn CMOS. simulation results show -3dB bandwidth 1.8GHz, maximum...

This paper proposes an energy-efficient intelligent pulmonary auscultation system for post COVID-19 era wearable monitoring. consists of a tightly coupled two-stage hybrid neural network (TC-TSHNN) model and corresponding multi-task training paradigm to improve prediction accuracy generalization ability based on the fact that number patients is far less than normal people. At first stage, two-category coarse classification performed identify abnormal lung sounds. If sound abnormal, second...

A new high precision CMOS current-mode band-gap voltage reference which takes advantage of the high-order curvature-compensated technique and enhancement pre-regulator is proposed. Based on 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> 0.35mum standard mixed-signal process technology, circuit achieves a much low temperature coefficient 3.68ppm/degC over range -40 degC to +150degC with 1.00V output PSRR broad frequency range. The...

With the growing interest of edge computing in Internet Things (IoT), Deep Neural Network (DNN) hardware processors/accelerators face challenges low energy consumption, latency, and data privacy issues. This paper proposes an energy-efficient processor design based on Belief (DBN), which is one most suitable DNN models for on- chip learning. In this study, a thorough algorithm-architecture-circuit optimization method used efficient design. The characteristics reuse sparsity DBN learning...

This paper presents a data non-destructive IMPLY-based memristive semi-parallel full-adder (FA) for Computing-in-memory system, which solves the issue that conventional FA cannot protect input operands. The proposed full adder not only reduce operating time by executing more steps in parallel, and also prevent operands from being destructed adding an extra memristor with one additional step. Simulation results show can realize 18% reduction on operation against design, while operand...

A voltage-controlled ring oscillator in 90nm CMOS technology with ultra wide-band and low phase noise for digital TV-tuner is presented. By introducing pre-amplifying transistors to get novel four outputs delay stage, tuning range greatly widened. Pre-charging optimized control method decrease without increasing parasitic capacitances. The can be operated from 38MHz 1.38GHz, while worst noises are −107dBc/Hz at 1MHz offset −85dBc/Hz 100 KHz full frequency range. It maximally consumes 11.1mA...