The next generation of multiprocessor system on chip (MPSoC) and multiprocessors (CMPs) will contain hundreds or thousands cores. Such a many‐core requires high‐performance interconnections to transfer data among the cores chip. Traditional components interface with interconnection backbone via bus interface. This can be an on‐chip multilayer architecture. With advent architectures, architecture becomes performance bottleneck framework. In contrast, network (NoC) promising communication...

This paper demonstrates the design and implementation of a real-time wireless physiological monitoring system for nursing centers, whose function is to monitor online status aged patients via communication channel wired local area network. The collected data, such as body temperature, blood pressure, heart rate, can then be stored in computer network management center facilitate medical staff real time or analyze batch mode changes under observation. Our proposed bidirectional, has low power...

A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. The BiNoC allows each communication be dynamically self-configured transmit flits in either direction order better utilize hardware resources. This added flexibility promises bandwidth utilization, lower packet delivery latency, and higher consumption rate at router. In this paper, a novel router supporting self-configuring bidirectional mechanism presented. It shown...

A novel Bidirectional Fault-Tolerant NoC (BFT-NoC) architecture capable of mitigating both static and dynamic channel failures is proposed. In a traditional platform, faulty data will force blocked packets to make costly detours, resulting in significant performance hits. this work, fault-tolerance measures for bidirectional platform are The dynamically reconfigurable channels the BFT-NoC offer great flexibility contain data-link permanent or transient faults while incurring negligible loss....

4G and other wireless systems are currently hot topics of research development in the communication field. Broadband based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present efficient implementation a pipeline FFT/IFFT processor for OFDM applications. Our design adopts single-path delay feedback style as proposed hardware architecture. To eliminate read-only memories (ROM's)...

A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication allows be dynamically self-reconfigured transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher consumption rate. Novel router developed support dynamic self-reconfiguration traffic flow. area-efficient BiNoC delivers requires smaller buffer size than...

Wheezing is a common clinical symptom in patients with obstructive pulmonary diseases such as asthma. Automatic wheezing detection offers an objective and accurate means for identifying lung sounds, helping physicians the diagnosis, long-term auscultation, analysis of patient disease. This paper describes design fast high-performance wheeze recognition system. A algorithm based on order truncate average method back-propagation neural network (BPNN) proposed. Some features are extracted from...

In emergency medical services, portable ultrasound scanners have the potential to become new-age stethoscopes for physicians. For trauma cases in particular, can scan chest and abdomen of patients both rapidly conveniently. This study describes development tele-ultrasound pre-diagnosis a setting as part updated Mobile Hospital Emergency Medical System (MHEMS). An technician provide an physician with patient's images information during pre-hospitalization transportation period using...

The CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with an auto-I/Q calibration function for IEEE 802.11g. supports I/Q gain and phase mismatch auto tuning mechanisms at both transmitting receiving ends, which are able reduce within 1/spl deg/ 0.1dB. Implemented in 0.25 /spl mu/m process 2.7 V supply voltage, delivers 5.1 dB receiver cascade noise figure, 7 dBm transmit, 1 compression point.

In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the minimization problem, incorporate an intermediate stage of layer/track assignment into framework. For performance-driven routing, minimum-radius minimum-cost spanning-tree (MRMCST) heuristic global routing. Compared with state-of-the-art experimental results show that our approach achieved 6.7X runtime speedup, reduced respective maximum average (coupling...

This paper describes the design of a low-cost and high performance wheeze recognition system. First, respiratory sounds are captured, amplified filtered by an analog circuit; then digitized through PC soundcard, recorded in accordance with Computerized Respiratory Sound Analysis (CORSA) standards. Since proposed detection algorithm is based on spectrogram processing sounds, spectrograms generated from have to pass 2D bilateral filter for edge-preserving smoothing. Finally, processed spectra...

In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the minimization problem, incorporate an intermediate stage of layer/track assignment into framework. For performance-driven routing, minimum-radius minimum-cost spanning tree heuristic global routing. Compared with state-of-the-art routability mode, experimental results show that our router achieved 6.7X runtime speedup, reduced respective maximum average...

As technology advances into the nanometer territory, antenna problem has caused significant impact on routing tools. The effect is a phenomenon of plasma-induced gate oxide degradation by charge accumulation conductors. It directly influences manufacturability and yield VLSI circuits, especially in deep-submicron using high density plasma. Furthermore, continuous increase size IC also great challenge to existing algorithms. In this paper, we propose novel framework for multilevel full-chip...

As technology advances into the nanometer territory, interconnect delay has become a first-order effect on chip performance. To handle this effect, X-architecture been proposed for high-performance integrated circuits. The presents new way of orienting chip's microscopic wires with pervasive use diagonal routes. It can reduce wirelength and via count, thus improve performance routability. Furthermore, continuous increase problem size IC routing is also great challenge to existing algorithms....

This paper presents a novel pipelined FFT/IFFT processor for OFDM applications. The proposed architecture employs low-complexity complex multiplier and constant to eliminate the need of ROM tables, thus consumes lower power than existing works. Finally, this design spends about 33.6K gates, consumption is 9.8mW at 20MHz.

The percentage of the elderly population grew rapidly in recent years, so tremendous life and health care needs became an issue focus aging society. Elderly Nursing Home plays important role intends to provide a comfortable environment living space serve as safe healthy place for elderly. However, frailty fragility both physiologically psychologically make it uneasy task. To enhance service quality Home, ubiquitous monitor system integrated with biosensors radio frequency identification...

This paper presents the architecture and implementation of a single-chip VLSI for two-dimensional discrete wavelet transform (2-D DWT) decomposition. nonseparable based uses parallel-systolic filter structure to compute all resolution levels DWTs, such that input samples can be processed at rate one sample per clock cycle. The chip was fabricated in 0.6 /spl mu/m CMOS technology packaged as 48-pin DIP. For computation an N/spl times/N still image with length L, this needs N/sup 2/+N cycles...

In this paper, we propose a parallel design of Viterbi decoder for Software-Defined Radio (SDR). Our method implements divide-and-conquer approach by tiling decoding sequences, performing independent speculated decoding, and merging partial candidate paths into the final path. For each best path is selected calculating Hamming distances trellis-by-trellis in parallel. shows up to 14.6x speedup on an NVIDIA 8800 GTX over sequential C implementation 2.4GHz Intel Core 2 CPU. Also, compared with...

Critical systems have very stringent requirements on both security and safety. Recent mishaps such as the missing MH370 aircraft sunk Korean Sewol ferry go to show that our technology in safety risk assessment still need a more integrated approach. Nuclear plant meltdown recent Fukushima accident is also typical example of insufficient assessments. This work case study how unified methodology may be applied High Pressure Core Flooder (HPCF) system nuclear power plant. Individual or...

In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the minimization problem, incorporate an intermediate stage of layer/track assignment into framework. For performance-driven routing, minimum-radius minimum-cost spanning-tree (MRMCST) heuristic global routing. Compared with state-of-the-art experimental results show that our approach achieved 6.7X runtime speedup, reduced respective maximum average (coupling...

The CMOS gate matrix layout problem is formulated and solved as an artificial intelligence planning in which a plan (the solution algorithm) to be generated achieve goal layout). overall consists of many subgoals, each corresponds the placement slot, routing associated nets connecting that gate. As different compete for track (resource) usage, these subgoals interact (interfere) with other, rendering suboptimal solutions. Here, such interaction among managed two techniques: hierarchical...

In this paper, the authors propose a novel high-throughput, ASIC architecture to realize context-adaptive variable-length decoder (CAVLC) of H.264/AVC baseline profile. The conduct thorough analysis inherent parallelism CAVLC algorithm and identify particular steps that will benefit from parallel computing. particular, adopt bit-position VLC decoding approach decode multiple symbols concurrently in critical step CAVLC. This modification leads almost 40% reduction clock cycles compared...

This paper describes a 5/spl times/5 window-based, power-of-two approximation algorithm for 2D Gaussian smoothing filter and its generic hardware reference design. With small change in standard deviation /spl sigma/, the is able to provide different levels of noise reduction capability, which highly desirable early stage an image processing flow. By using terms, digital-approximated can be implemented by simple shifters. A design also proposed achieve such functionality. Experiments with...

Given a die with I/O pads wire bonded onto the multilayer substrates of pin grid array (PGA) package, three-step net-even-wiring system (NEWS) is proposed to complete routing bond corresponding pins on one or more layers. First, we performed maximum-cut partitioning net interference graph for layer assignment step. Second, nets each were converted planar sketches using novel insertion sort method. Last, transformed into net-even-wired layout simplified rubber-band router.