A5085139879- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Quantum-Dot Cellular Automata
- Computational Drug Discovery Methods
- Analog and Mixed-Signal Circuit Design
- Genetics, Bioinformatics, and Biomedical Research
- vaccines and immunoinformatics approaches
- SARS-CoV-2 and COVID-19 Research
- COVID-19 Clinical Research Studies
- Brain Tumor Detection and Classification
- ECG Monitoring and Analysis
- Cell Image Analysis Techniques
- EEG and Brain-Computer Interfaces
- Endodontics and Root Canal Treatments
- Enzyme function and inhibition
- Peptidase Inhibition and Analysis
- Advanced Technology in Applications
- Image Enhancement Techniques
- Protein Degradation and Inhibitors
- Technology and Data Analysis
- Chaos-based Image/Signal Encryption
- Automated Road and Building Extraction
- Computer Graphics and Visualization Techniques
- Advancements in Materials Engineering
- Big Data and Business Intelligence
Madhya Pradesh Bhoj Open University
2024-2025
Barkatullah University
2022-2025
Ragas Dental College & Hospital
2022
Maulana Azad National Institute of Technology
2018-2021
Indian Institute of Information Technology Allahabad
2021
Beijing University of Posts and Telecommunications
2017
National Institute of Technology Tiruchirappalli
2013
With the miniaturization of digital integrated circuits, electronic systems with increased functionality and enhanced performance are preferred. Multi-valued logic design is a promising alternative that offers higher number data/information which leads to energy efficiency, information density reduced circuit overheads in terms interconnect complexity. Hence this work multi-valued benefits computational capability complexity being explored for implementation sequential elements viz. ternary...
Multi-valued logic design provides the benefit of increased integration by reducing interconnections which is main source power dissipation in VLSI chip. As compared to conventional binary representation, ternary representation helps represent more amount information over same number digits. Hence this work presents adder, subtractor, multiplier and parallel adder/subtractor with enhanced performance carbon nanotube field effect transistor (CNFET) technology. The addition subtraction...
This paper presents a very low power and area efficient ASIC implementation of Advanced Encryption Standard Algorithm (AES). The results S-Box, MixColumn Transformation overall AES encryption/ decryption are given in this paper. has been implemented 90nm standard CMOS library using Synopsys Design Compiler with core voltage 1.2V. dissipation S-Box is 16.2 μW at 10 MHz clock frequency. Total AES-128 bit 224 50377 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
An unusual pneumonia infection, named COVID-19, was reported on December 2019 in China. It to be caused by a novel coronavirus which has infected approximately 8.7 million people worldwide with death toll of 463000 till date. This study is focused finding potential vaccine candidates and designing an in-silico subunit multi-epitope using unique computational pipeline, integrating reverse vaccinology molecular docking methods. A protein SARS-CoV-spike [S] SARS-CoV-2 having GenBank ID-...
This work presents the contemplate review of diverse approaches employed to design XOR/XNOR circuits, as these circuits are nucleus circuit for numerous computational intensive arithmetic in VLSI. paper describes comparative analysis performance evaluation various reported XOR and XNOR designs. The different designs compared by performing transistor level simulations on benchmark using HSPICE 90nm PTM CMOS technology analyzing results comprehensive manner. Based simulations, with feedback...
Differential cascode voltage switch (DCVS) is a static technique which offers the advantages of layout density, logic flexibility together with improved delay and power consumption. In this study, DCVS-based ternary gates unary operators are reported using diode divider topology. The main focus proposed designs DCVS style to provide minimum energy consumption less area overhead. presented method, new efficient compact solution being provided improve driving capability circuits. All...
Ternary logic is a promising alternative to classical binary as it offers the benefits of reduced interconnect, higher operating speed and smaller chip area. In this paper, new approach proposed implement 3–2 compressor 4–2 circuits using futuristic carbon nanotube field-effect transistors (CNTFET). A CNTFET unique feature geometry dependent threshold variation utilized in detector which have been used perform ternary conversion. The high power consumption capacitive based designs by...
The usage of ternary logic in the digital design leads to reduction interconnect complexity and chip area which helps improve circuit performance various applications. This work presents realization flip flop structures using Min./Max. operators. implementation is based on carbon nanotube field effect transistors having exceptional electrical characteristic threshold voltage variations by employing CNTs with different diameters. three-valued benefit enhanced processing capability employed...
Background: One of the main purposes root canal treatment is complete debridement canals. Regardless instrumentation technique used 35% or more surfaces have been observed to remain uninstrumented. To remove debris and address these uninstrumented surfaces, it necessary copiously irrigate canal. Many adjuncts also developed being in an effort improve delivery effectiveness irrigants. Although much research conducted on different regime irrigants dentistry, only a little data can be found...