A5101665635- Interconnection Networks and Systems
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Advanced Memory and Neural Computing
- Particle Detector Development and Performance
- CCD and CMOS Imaging Sensors
- Advanced Vision and Imaging
- Image Enhancement Techniques
- Video Coding and Compression Technologies
- Distributed and Parallel Computing Systems
- Analog and Mixed-Signal Circuit Design
- Radiation Detection and Scintillator Technologies
- Supercapacitor Materials and Fabrication
- Radiation Effects in Electronics
- Image and Video Quality Assessment
- Advanced Image Processing Techniques
- VLSI and Analog Circuit Testing
- Advanced Data Compression Techniques
- Remote Sensing and LiDAR Applications
- Advanced Data Storage Technologies
- Distributed systems and fault tolerance
- Digital Filter Design and Implementation
- Autonomous Vehicle Technology and Safety
- Color Science and Applications
- Atomic and Subatomic Physics Research
Harbin Institute of Technology
2015-2025
Aerospace Institute (Germany)
2019-2020
Heilongjiang Institute of Technology
2018-2020
Nanchang University
2004
Abstract “A Craftsman Must Sharpen His Tools to Do Job,” said Confucius. Nuclear detection and readout techniques are the foundation of particle physics, nuclear astrophysics reveal nature universe. Also, they being increasingly used in other disciplines like power generation, life sciences, environmental medical etc. The article reviews short history, recent development, trend techniques, covering Semiconductor Detector, Gaseous Scintillation Cherenkov Transition Radiation Readout...
Vision-based unstructured road following is a challenging task due to the nature of scene. This paper describes novel algorithm improve accuracy and robustness vanishing point estimation with very low computational cost. The novelties this are three aspects: 1) We use joint activities four Gabor filters confidence measure for speeding up process texture orientation estimation. 2) Misidentification chances complexity reduced by using particle filter. It limits search range reduces number...
Journal Article Stabilization of quasi-one-sided Lipschitz nonlinear systems Get access Fengyu Fu, Fu * Center for Control Theory and Guidance Technology, Harbin Institute 150001, China *Corresponding author: fufengyu2002@163.com Search other works by this author on: Oxford Academic Google Scholar Mingzhe Hou, Hou Guangren Duan IMA Mathematical Information, Volume 30, Issue 2, June 2013, Pages 169–184, https://doi.org/10.1093/imamci/dns023 Published: 11 August 2012 history Received: 25...
In the post-Moore era, excessive amount of information brings great challenges to performance computing systems. To cope with these challenges, approximate computation has developed rapidly, which enhances system minor degradation in accuracy. this paper, we investigate utilization an Artificial Intelligence Things (AIoT) processor for computing. Firstly, employed neural architecture search (NAS) acquire network structure computation, approximates functions FFT, DCT, FIR, and IIR....
In advanced multicore embedded systems, network-on-chip (NoC) is vital for core communication. With a rise in the number of cores, incidence failures rises, potentially affecting system performance and stability. To address challenges associated with researchers have proposed numerous topology reconfiguration algorithms. However, these algorithms fail to achieve an optimal balance between rate recovery time. Addressing issues, we propose adaptive distribution optimization algorithm, which...
In this paper, we present an AXI compliant Network Interface (NI) for NoC, which can deal with the reordering problem and support adaptive routing. On basic of analyzing necessity feasibility packet reordering, propose a novel mechanism based on look up table, guarantee globally ordering response transactions. Our NI (NISAR) also supports master slave core together. The average latency introduced by NISAR is 3-4 cycles, throughput achieves to 0.87 flits/cycle random transaction length...
As the leading research platform of heavy-ion science in China, physics and applications at Heavy Ion Research Facility Lanzhou (HIRFL) High-Intensity Accelerator (HIAF) drive development new detector technology. A monolithic active pixel sensor (MAPS) has been designed a 130-nm CMOS process for HIRLF HIAF. This MAPS can measure energy deposition position particle hit. critical component this MAPS, regional 12-bit 40-Msps pipeline ADC to convert analog signals from pixels into digital data....
A flexible and efficient programming model for NoC-Based MPSoC, MMPI (Multiprocessor Message Passing Interface) is proposed. To improve the efficiency of design exploration, separates parallel-programming from iterative exploration process by introducing a "mapping file" mechanism defining layered communication protocol stack. Both spacial parallelism temporal are supported to resource utilization performance. The results demonstrate that achieves small memory execution footprints, resolves...
Using a hybrid main memory in embedded systems to process image processing applications has become an irresistible trend. However, the performance deficiencies (less write endurance and relative longer latency) phase change (PCM) have bottleneck for improvement whole system. To further improve system, data migration schemes been put forward migrate sequential between DRAM PCM. Nevertheless, existing are always universal type page schemes, which cannot be aware of hot pages accurately. In...
An Objective-Flexible Clustering Algorithm (OFCA), which is applicable to multiple design objectives and targets high performance low energy task mapping scheduling on homogenous cluster-based NoC, presented. OFCA employs a lineal clustering group tasks into clusters, utilizes an efficient heuristic process allocate ready clusters onto the platform. Then latency pipeline-based static stage proposed arrange sequence in IP cores. Finally best hardware resource demand for application could be...
Abstract The Monolithic Active Pixel Sensor (MAPS) is a good candidate for the inner tracking system of Electron–Ion Collider in China (EicC). Hence, MAPS with pixel pitch ∼30 µm being designed. Two 130 nm CMOS processes have been proposed as candidates this design. first one commercial standard twin-well low-resistivity (<50 Ω cm −3 ) process, and other quadruple-well high-resistivity (>1 kΩ process. A 3-dimensional TCAD model pixels has established to evaluate Minimum Ionizing...
Abstract The High Intensity heavy-ion Accelerator Facility (HIAF) is being constructed to generate intense beams of primary and radioactive ion for a wide range research fields. Hence, Monolithic Active Pixel Sensor (MAPS) named Nupix-A2 has been developed in 130-nm Resistivity CMOS process. can simultaneously measure the particle hit' energy, arrival time, position. It consists 128 × pixel array, digital-to-analog converter digital control module. energy deposition from 300 e- over 50 ke-...
Virtual channel (VC) flow control proves to be an alternative way promote network performance, but uniform VC allocation in the may at cost of chip area and power consumption. We propose a novel number algorithm customizing VCs based on characterist
Task migration, an effective resource management approach, contributes to increase of on-chip communication overhead. We propose MMPI-based task migration mechanism lower overhead in NoC-based MPSoC. This depends on MPSoC message passing interface (MMPI), which defines a parallel programming pattern that program is dependent mapping. In the mechanism, state information transferred another PE. The lowered since based MMPI and code not transferred. Furthermore, does require checkpoints detect...
A small-granularity solution with high performance and low area cost for fault-tolerant routing of hard error in 2D-Mesh Network-on-Chip is proposed. This presents a new fault model, defines separately node-fault link-fault, reduces situations classified as effectively, consequently improves the network. By defining some paths to substitute failure paths, data packets can be routed along which are formed by neighbor nodes or link-fault. Finally, wormhole router based on XY algorithm designed...
Phase change memory (PCM) and DRAM-based hybrid main have emerged as one of the most promising technology for future embedded systems. Previous research works focused on page migration strategies to fully exploit advantages DRAM PCM achieve higher performance energy efficiency. However, ability predict pages’ behavior in these could be further improved do not consider how reduce consumption decrease system energy. In this article, we propose a novel dynamic hardware strategy named periodical...
Most streaming applications, such as multimedia and digital signal processing (DSP) application, are iterative in nature, so pipelined implementation can be introduced into application for high throughput. In this case, a communication-centric design approach, NoC is capable of solving communication bottleneck incurred by throughput increment. paper with was mapped onto the architecture an energy-aware mapping algorithm proposed focusing on pipelining mechanism. This performs task...
Network-on-Chip (NoC) has been proposed as a new solution to deal with the global communication problem of complex System-on-Chip (SoC), which faces huge design challenges. A performance evaluation tool is essential for designers explore space, verify functionality and estimate designs. This paper presents platform NoC, can measure present NoC designs at transaction-level, register-transfer-level application-level abstraction. Based on hierarchical progressive abstraction approach, built...
A novel reconfigurable 2D mesh Network-on-Chip (NoC) architecture (REmesh) and a topology reconfiguration algorithm (TRARE) are proposed in this paper. Compared with conventional mesh, REmesh, which employs few more routers multiplexers, can be easily reconfigured to restore tolerant core faults NoCs. Based on TRARE repeatedly categorizes routers, connects cores eventually finds out solution. Simulation results show that the topologies sizes do not exceed 7×8, than 90% successful rate...