A5085948014- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- CCD and CMOS Imaging Sensors
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Data Storage Technologies
- Thin-Film Transistor Technologies
- Analytical Chemistry and Sensors
- Neuroscience and Neural Engineering
- Infrared Target Detection Methodologies
- Image Processing Techniques and Applications
- Silicon Nanostructures and Photoluminescence
- Nanowire Synthesis and Applications
- Advancements in Photolithography Techniques
- Silicon Carbide Semiconductor Technologies
- Gas Sensing Nanomaterials and Sensors
- Electrostatic Discharge in Electronics
- 3D IC and TSV technologies
- Low-power high-performance VLSI design
- Copper Interconnects and Reliability
- Plasma Diagnostics and Applications
- Electron and X-Ray Spectroscopy Techniques
- Advanced Optical Sensing Technologies
- Analog and Mixed-Signal Circuit Design
National Tsing Hua University
2015-2024
Lite-On Technology Corporation (Taiwan)
2017
United Microelectronics (Taiwan)
2016
Tsinghua University
2016
Taiwan Semiconductor Manufacturing Company (Taiwan)
2010
Macronix International (Taiwan)
2007-2009
Institute of Electronics
2007
University of California, Berkeley
1995-2005
Many artificial intelligence (AI) edge devices use nonvolatile memory (NVM) to store the weights for neural network (trained off-line on an AI server), and require low-energy fast I/O accesses. The deep networks (DNN) used by processors [1,2] commonly p-layers of a convolutional (CNN) q-layers fully-connected (FCN). Current DNN that conventional (von-Neumann) structure are limited high access latencies, energy consumption, hardware costs. Large working data sets result in heavy accesses...
Embedded nonvolatile memory (NVM) and computing-in-memory (CIM) are significantly reducing the latency (t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAC</inf> ) energy consumption (E of multiply- and-accumulate (MAC) operations in artificial intelligence (AI) edge devices [1, 2]. Previous ReRAM CIM macros demonstrated MAC for lb-input, ternary- weighted, 3b-output CNNs [1] or 8b-weighted, 1b-output fully-connected networks with limited...
In this work, we describe a novel technique of fabricating germanium nanocrystal quasi-nonvolatile memory device. The device consists metal-oxide-semiconductor field-effect transistor (MOSFET) with Ge charge-traps embedded within the gate dielectric. trap formation method provides for precise control thicknesses top (control) and bottom (tunneling) oxide layers which sandwich charge-traps, via thermal oxidation. This exhibits write/erase speed/voltage retention time superior to previously...
This paper presents an integrated vibration power generator system. The system consists of a mini electromagnetic and highly efficient energy harvesting circuit implemented on minute printed board 0.35-mum CMOS chip. By introducing feedback control into the dc-dc pulsewidth modulation (PWM) boost converter with feedforward control, can adjust duty ratio following variation input voltage storage element to get high conversion efficiency. rectifies ac voltage, steps up dc output rectifier by...
A new type of true random number generator, based on the telegraph noise a contact-resistive access memory device, is proposed in this letter. The random-number generator consists only simple bias circuit plus comparator, leading to small area and low power consumption. By realizing by 65-nm complementary metal-oxide-semiconductor logic process, occupied can be as 45 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , demonstrating...
Resistive RAM (ReRAM) is a promising nonvolatile memory with low write energy, logic-process compatibility, and compact cell area. The 1T1R ReRAM [1-3] fits embedded applications requiring fast read (RD) access time (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AC</inf> ) RD-V xmlns:xlink="http://www.w3.org/1999/xlink">DDMIN</inf> , particularly for devices powered by batteries or energy harvesters. cross-point [4-6] meant high capacities...
With the rising importance of energy efficiency, zero leakage power and instant-on capability are highly desired features in harvesting sensors, as well “normally off” high performance processors. However, intermittent such systems requires nonvolatile memory (NVM) to hold intermediate data avoid rollbacks. Previous work has adopted FeRAM STT-MRAM achieve zero-standby fast-restore processors (NVPs) [1–3]. NVPs, however, suffer from several drawbacks: 1) Various interrupt periods not...
Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices. However, circuit design NVM-based CIM (nvCIM) imposes number of challenges, including an area-latency-energy tradeoff multibit MAC operations, pattern-dependent degradation signal margin, and small read margin. To overcome these this article proposes the following: 1) serial-input non-weighted...
Decreasing read cell current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">CELL</sub> ) has become a major trend in nonvolatile memory (NVM). However, reduced leaves the operation of sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- NVMs suffer from slow speed or low yield. In this study, we propose new current-sampling-based (CSB-SA) suppress...
Numerous low-supply-voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) mobile chips, such as energy-harvesting-powered devices and biomedical applications, require low-V on-chip nonvolatile memory (NVM) for low-power active-mode access power-off data storage. However, conventional NVMs cannot achieve operation due to insufficient write voltage generated by charge-pumped (CP) circuits at a low V , lack of current-mode sense...
As the gate oxide thickness decreases below 2 nm, leakage current increases dramatically due to direct tunneling current. This large will be an obstacle reducing for high speed operation of future devices. A MOS transistor with Ta/sub 2/O/sub 5/ dielectric is fabricated and characterized as a possible replacement transistors ultra-thin silicon dioxide. Mobility, I/sub d/-V/sub d/, g/, current, capacitance-voltage (C-V) characteristics are evaluated compared SiO/sub 2/ transistors. The three...
Ternary content-addressable memory (TCAM) is used in search engines for network and big-data processing [1]–[6]. Nonvolatile TCAM (nvTCAM) was developed to reduce cell area (A), energy (ES), standby power beyond what can be achieved using SRAM-based (sTCAM) [1]–[2]: particularly applications with long idle times frequent-search-few-write operations. nvTCAMs were previously designed diode-4T2R (D4T2R) STT-MTJ [3], 2T2R phase-change [4], 4T2R 3T1R ReRAM [5,6]. However, these NV devices suffer...
In this paper, we present an ultra high density 3D Via RRAM with 28nm HKMG CMOS fully compatible process. It is the first time to report a cross-point formed by stacked 30nm × Cu and metal line of single damascene The cell consists TaON-based resistive film, as top electrode, bottom electrode. film composite layer backend glue Ta TaN in Moreover, compact structure, unit area cell-string reduced only 4 times size design rules. Since fabricated without extra TMO or process step, excellent...
Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energy-efficient systems. However, this technology is limited with regard to speed, power, VDDmin, yield due process variation transistors memrisitive as well the issue of read disturbance. This paper examines trends design device using challenges faced by researchers its further development. Several silicon-verified examples circuitry are reviewed paper, including those aimed at...
We investigated the influence of passivation-layer deposition on characteristics a-InGaZnO thin-film transistors (TFTs). The threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> ) TFTs shifted markedly as a result mechanical stress induced by passivation layers above. By adjusting parameters during process, performance can be modulated. after dual exhibited good with field-effect mobility 11.35 cm <sup...
A new three dimensional vertical bipolar junction transistor (BJT) ReRAM cell with CMOS compatible process is reported. logic BJT vertically formed underneath the resistive stacked film of TiN/Ti/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN as a high performance current driver and bit-cell selector. Using shallow tiny NLDD to be an emitter connects bitline, very thin self-aligned P-pocket implant wordline, N-well collector...
Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large store energy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{E}_{\mathrm {S}}$ </tex-math></inline-formula> )...
Simple quantitative models of charge displacement due to the quantum effect and its influence on gate oxide thickness measurements are presented. An effective (T/sub DC/) is introduced which relevant MOSFET current modeling. Physical T/sub DC/ can be extracted easily from capacitance measurement, electrical predicted a target physical using these new models.
Single electron trapping/de-trapping behavior is firstly observed and investigated in the contact resistive random access memory cell. By analyzing telegraph noise, temperature-dependency of resistance levels high-temperature data retention RRAM film are successfully explained. Detail analyses on capture emission electrons this cell provide further verifications for proposed trap-induced switching model.
A new high density Contact RRAM (CRRAM) cell realized in pure high-k metal gate 28nm CMOS logic process with a very small 35nm×35nm resistive contact hole has been fabricated without extra masking or step. This study reports the first time of manufacturable tiny node on platform and fully compatible processes. The exhibits stable operation window size 0.03μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Due to scale down uniform...
The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> technology that shows wake-up free character, 10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> /10 xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> endurance cycles, extrapolated 10-year retention at 105°C/85°C,...
A novel logarithmic response CMOS image sensor fabricated by 0.25-/spl mu/m logic process is proposed. The new cell has an output voltage swing of 1 V in the targeted illumination range, which makes it less susceptible to noises readout system. Furthermore, proposed with in-pixel CDS control drastically reduces fixed pattern noise mode APS. Comparing a conventional pixel, reduction 10 times fixed-pattern demonstrated sensor.
Theoretical calculation indicates that when the fin width is comparable to EOT of ONO, bottom oxide electric field around tip significantly increased, resulting in enhanced program/erase efficiency. We also discover non-uniform injection along changes DC characteristics (S.S. and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) during program/erase, effective channel FinFET SONOS only tip. integrate BE-SONOS a body-tied structure with...
In this letter, charge-based capacitance measurement (CBCM) is applied to characterize bias-dependent capacitances in a CMOS transistor. Due its special advantage of being free from the errors induced by charge injection, operation charge-injection-induced-error-free CBCM allows for extraction full-range gate accumulation region inversion and overlap MOSFET devices with submicrometer dimensions.