Low-cost optical receivers (RX) operating at 100+ Gb/s 4-PAM with low power are in high demand to support 400GBASE-DR4/FR4 links data centers. Existing pluggable solutions generally realize the RX front-end BiCMOS. However, a more integrated solution, front-ends onto CMOS host IC and co-packaged alongside photodiodes (PDs), offers potential for smaller size, lower cost, [1], [2]. This work demonstrates 112 linear TIA flip-chip commercial PDs different PD-to-RX interconnect lengths (Fig. 1a).

This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to sources as well body of critical sensing transistors. We simulated and fabricated proposed DIBBSA architecture various operational modes in 65-nm CMOS technology analyze biasing's effectiveness mitigating offset. The standard deviation offset ( σ <sub...

A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with −8.2-dBm sensitivity is presented support for optical receivers required the next-generation intra-data center links. proposed three-stage TIA comprised of a shunt-feedback stage followed by digitally programmable continuous-time equalizers (CTLEs) and variable gain (VGA). Broadband low-noise design achieved...

Sense amplifier (SA) input-referred offset often dictates the minimum required differential input ($\Delta V_{\textrm {BL-min}}$ ) and is an important factor in realizing low-voltage static random access memories. This paper presents a HYbrid latch-type Amplifier (HYSA-QZ), where bitline signals are supplied to multiple internal nodes significantly reduce $\Delta . A 65-nm CMOS test chip with arrays of HYSA-QZ, two intermediate formulations conventional current latch SA (CLSA), voltage...

An offset tolerant SRAM sense amplifier (SA) deployed with sample-boost-latch technique to facilitate both common mode and differential boosting is proposed. The enables proposed SA, SBLSA operate deeper into the subthreshold regime whereas helps tolerate undesirable mismatch conditions by driving cross-coupled inverters boosted voltages. circuit first samples bitline voltages then isolates sampled from highly capacitive bitlines followed phase on relatively much less internal input...

The problem of finding the optimal number phased array faces for performing hemispheric volume surveillance is considered. Assuming detection performance same in all beam positions and total modules are constant, it shown that three. This true when coverage extends to zenith 45/spl deg/ elevation. It also whether operating simultaneously or sequentially.

The problem of the optimal number phased array faces for performing 360/spl deg/ horizon surveillance is considered. Assuming detection performance same in all beam positions and total T/R modules constant, it shown that three. This true whether arrays are operating simultaneously or sequentially.

The problem of the optimal number phased array faces for performing 360/spl deg/ horizon surveillance is considered. Assuming detection performance same in all beam positions and total T/R modules constant, it shown that three. This true whether arrays are operating simultaneously or sequentially. A parametric analysis performed between associated cost simultaneous operation terms size array.

Variability in offset voltage, bitcell transistor conductance, and leakage currents can lead to marginal intermittent failures low-voltage SRAMs. In this paper, we develop a model of these faults that includes such sense amplifier variability. Using simulations measurement data from 65 nm test chip, investigate the likelihood propose how stimulate their occurrence during testing.

This paper addresses the optimization of interface between photodetector (PD) and analog front-end (AFE) in high-speed, high-density optical communication receivers. Specifically, focuses on optimizing design elements interface, including interconnecting transmission line, T-coil, transimpedance amplifier (TIA), digital equalization tap weights. To optimize link, we use a combination analytical models, electromagnetic simulations (EM), machine learning (ML) techniques to describe different...