A5043629600- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Optimal Power Flow Distribution
- Power System Optimization and Stability
- Electric Power System Optimization
- Integrated Circuits and Semiconductor Failure Analysis
- Microgrid Control and Optimization
- Particle Accelerators and Free-Electron Lasers
- Advanced Memory and Neural Computing
- VLSI and Analog Circuit Testing
- Particle accelerators and beam dynamics
- Analog and Mixed-Signal Circuit Design
- Radiation Effects in Electronics
- HVDC Systems and Fault Protection
- Topic Modeling
- Electric Motor Design and Analysis
- Laser-induced spectroscopy and plasma
- Advanced Battery Technologies Research
- Energy Load and Power Forecasting
- Power Quality and Harmonics
- Atomic and Molecular Physics
- Biomedical Text Mining and Ontologies
- Electric and Hybrid Vehicle Technologies
- Parallel Computing and Optimization Techniques
Bharati Vidyapeeth Deemed University
2023-2025
Vellore Institute of Technology University
2025
Delhi Technological University
2018-2023
Raja Ramanna Centre for Advanced Technology
2000-2021
Krishna Institute of Medical Sciences
2021
Broadcom (United States)
2016-2018
Broadcom (Israel)
2013-2015
University of Minnesota
2010-2013
Intel (United States)
2004
Abstract Emerging sub-synchronous interactions (SSI) in wind-integrated power systems have added intense attention after numerous incidents the US and China due to involvement of series compensated transmission lines electronics devices. SSI phenomenon occurs when two system elements exchange energy below synchronous frequency. related wind plants is one most significant challenges maintaining stability, while practical farms, which has been observed recently, not yet described on source...
This paper introduces a novel approach to enhance the control algorithm for single-phase shunt active power filter(SAPF) by integrating new technique into 5-level cascaded multilevel inverter (MLI) with Photo Voltaic (PV) array integration. Due integration of non-linear loads in grid, such as computers, variable speed drives, and other solid-state equipment, non-sinusoidal currents are drawn, introducing harmonics that distort voltage current waveforms. It is essential mitigate these...
Abstract Low-frequency oscillations (LFO) are inherent to large interconnected power systems. Timely detection and mitigation of these is essential maintain reliable system operation. This paper presents a methodology identify mitigate low-frequency ( forced inter-area) using wide area monitoring (WAMS) based model utilizing phasor measurement units (PMUs). These models accurately the behavior location generators contributing in real-time hence can efficiently improve performance WADC them....
SRAM SER measurements across technology nodes indicate that while scaling from planar to the first FinFET process provided a large reduction in per-bit SER, subsequent within results comparable cell area reduction. Extensive over range of voltages show strong exponential increase processes with bias, compared linear bias dependence for process.
This paper offers three easy-to-use metaphor-less optimization algorithms proposed by Rao to solve the optimal power flow (OPF) problem. are parameter-less algorithms. As a result, algorithm-specific parameter tuning is not required at all. quality makes these simple use and able various kinds of complex constrained engineering problems. In this paper, main aim OPF problem find values control variables in given electrical network for fuel cost minimization, real losses emission voltage...
Efficient wealth management in dynamic financial environments is crucial for maximizing returns and mitigating risk. Therefore, this study presents an adaptive portfolio strategy that combines momentum-based clustering, a Proportional-Integration-Derivative (PID) controller, efficient frontier (EF) analysis to construct optimal portfolios environments. A novel integration of PID controller dynamically adjusts the asset weights address limitations static optimization methods. EF then employed...
A new hybrid meta-heuristic approach Jaya–PPS, which is the combination of Jaya algorithm and Powell’s Pattern Search method, proposed in this paper to solve optimal power flow (OPF) problem for minimization fuel cost, emission real losses total voltage deviation simultaneously. The recently developed has been applied exploration search space, while excellent local capability PPS (Powell’s Search) method used exploitation purposes. Integration procedure into classical was carried out three...
Dual- and triple-well bulk CMOS SRAMs fabricated at the 28-nm node were tested using alpha particles heavy-ions over a range of supply voltages. Dual-well have better Multiple Cell Upset (MCU) cross sections spread for nominal voltage, while are reduced TCAD simulations show that single-event upset reversal due to charge confinement is responsible improved soft error rate (SER) performance low voltage operation SRAMs.
This article presents a novel scheme for saving architectural power by mitigating delay degradations in digital circuits due to bias temperature instability (BTI), inspired the notion of human circadian rhythms. The method works two alternating phases. In first, compute phase, circuit is awake and active, operating briskly at greater-than-nominal supply voltage which causes tasks complete more quickly. second, idle power-gated put sleep, enabling BTI recovery. Since wakeful stage an elevated...
The effect of oxide soft breakdown (SBD) on the reliability a 6-T cache cell has been examined and circuit based gate (GOX) model developed. results show that combines topology, PMOS bias temperature (PMOS BT) effect, SBD time dependent leakage allows for accurate prediction observed vccmin test voltage dependence. Through simulation it was determined BT plays significant role in aggravating effects stability. Examples are shown stability using simplified including varying amounts...
SRAM physical unclonable function (PUF) provides a low-cost security key to address hardware attacks such as cloning well for reliability tracking of ICs in the field. In this work quality and aging 28 nm high-K metal gate planar 16 FinFET based SRAMs are discussed detail with regards their use PUF. Data indicates that process has better PUF without any design modifications compared process. addition, aging-induced bit instability is shown be reasonably small percentage overall counts.
Optimal power flow solutions are required for the cost-effective operation and control of an existing system as well its future expansion planning. In this paper, a hybrid meta-heuristic Jaya-Powell's Pattern Search method is proposed to solve optimal problem integrated with distributed generating units. Powell's has been incorporated into Jaya algorithm in three different ways, resulting variants namely; Jaya-PPS1, Jaya-PPS2, Jaya-PPS3. Performance these evaluated by solving IEEE 30-bus,...
State-of-the-art timing tools are built around the use of current source models (CSMs), which have proven to be fast and accurate in enabling analysis large circuits. As circuits become increasingly exposed process temperature variations, there is a strong need augment these account for thermal effects impact adaptive body biasing, compensatory technique that used overcome on-chip variations. However, straightforward extension CSMs incorporate at multiple biases temperatures results...
This paper presents a novel scheme for mitigating delay degradations in digital circuits due to bias temperature instability (BTI). The method works two alternating phases. In the first, greater-than-nominal supply voltage, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd,g</sub> is used, which causes task complete more quickly but greater aging than nominal xmlns:xlink="http://www.w3.org/1999/xlink">dd,n</sub> . second, circuit power-gated,...
In the period of extreme CMOS scaling, reliability issues are becoming a critical problem. These problems include related to device reliability, in form bias temperature instability, hot carrier injection, time-dependent dielectric breakdown gate oxides, as well interconnect concerns such electromigration and TSV stress 3D integrated circuits. This tutorial surveys these effects, discusses methods for mitigating them at all levels design.
In this paper, a mathematical model based on COVID-19 is developed to study and manage disease outbreaks. The effect of vaccination with regard its efficacy percentage population vaccinated in closed investigated. To virus transmission, the system employs six nonlinear ordinary differential equations susceptible–exposed–asymptomatic–infected–vaccinated–recovered populations basic reproduction number are calculated. proposed describes for highly infectious diseases (such as COVID-19)...