A5000307027- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Ferroelectric and Negative Capacitance Devices
National Yang Ming Chiao Tung University
2023
This article proposes a memory cell, denoted by 1F-1T, consisting of ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting (T). The reduces the impact drain current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$I_{d}$</tex-math></inline-formula> ) variations limiting on-state in FeFET. experimental data from our 28nm high-k-metal-gate (HKMG) based FeFET calibrates and...
Harnessing multibit precision in nonvolatile memory (NVM)‐based synaptic core can accelerate multiply and accumulate (MAC) operation of deep neural network (DNN). However, NVM‐based cores suffer from the trade‐off between bit density performance. The undesired performance degradation with scaling, limited precision, asymmetry associated weight update poses a severe bottleneck realizing high‐density core. Herein, 1) evaluation novel differential mode ferroelectric field‐effect transistor...
Harnessing multibit precision in non-volatile memory (NVM) based synaptic core can accelerate multiply and accumulate (MAC) operation of deep neural network (DNN). However, NVM-based cores suffer from the trade-off between bit density performance. The undesired performance degradation with scaling, limited precision, asymmetry associated weight update poses a severe bottleneck realizing high-density core. In this work, we demonstrate: (i) implementation novel differential mode ferroelectric...
<p>This letter proposes a memory cell, denoted by 1F-1T, consisting of ferroelectric field-effect transistor (Fe-FET) cascoded with another current-limiting (T). The reduces the impact drain current (Id) variations limiting on-state in FeFET, 1F. We have fabricated 28nm high-k-meta-gate (HKMG) based FeFETs, and experimental data is used to model simulate single-cell arrays. simulation shows significant improvement bit-line (BL) (IBL ) variation for 1F-1T array. Finally, system-level...
This paper reports that large polarization <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(2\mathrm{P}_{\mathrm{r}}\approx 35.3\ \mu\mathrm{C}/\text{cm}^{2})$</tex> can be demonstrated in Si-doped Hf02 Metal-Ferroelectric-Insulator-Semiconductor Capacitors with proper annealing temperature. In addition, wake-up free characteristic as well good retention for up to 10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> seconds is observed...
<p>This letter proposes a memory cell, denoted by 1F-1T, consisting of ferroelectric field-effect transistor (Fe-FET) cascoded with another current-limiting (T). The reduces the impact drain current (Id) variations limiting on-state in FeFET, 1F. We have fabricated 28nm high-k-meta-gate (HKMG) based FeFETs, and experimental data is used to model simulate single-cell arrays. simulation shows significant improvement bit-line (BL) (IBL ) variation for 1F-1T array. Finally, system-level...