A5061978117- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Radio Frequency Integrated Circuit Design
- Nanowire Synthesis and Applications
- MXene and MAX Phase Materials
- Low-power high-performance VLSI design
- Analog and Mixed-Signal Circuit Design
- Silicon Carbide Semiconductor Technologies
- Photonic and Optical Devices
- Advanced MEMS and NEMS Technologies
- GaN-based semiconductor devices and materials
- Acoustic Wave Resonator Technologies
- Advancements in Photolithography Techniques
- Quantum and electron transport phenomena
- Electrostatic Discharge in Electronics
- Advanced Sensor and Energy Harvesting Materials
- VLSI and Analog Circuit Testing
- Near-Field Optical Microscopy
- Force Microscopy Techniques and Applications
GlobalFoundries (Germany)
2017-2025
CEA LETI
2016-2017
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2016-2017
Institut de Microélectronique, Electromagnétisme et Photonique
2012-2016
Université Grenoble Alpes
2015-2016
Institut polytechnique de Grenoble
2012-2016
Centre National de la Recherche Scientifique
2015-2016
Direction de la Recherche Technologique
2016
Micro and Nanotechnology Innovation Centre
2012
22FDX™ is the industry's first FDSOI technology architected to meet requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves power performance efficiency a 16/14nm FinFET in cost effective, planar device architecture that can be implemented with ~30% fewer masks. Performance comes from second generation transistor, which produces nFET (pFET) drive currents 910μ/μm (856μ/μm) at 0.8 V 100nA/μm Ioff. For ultra-low applications, it offers low-voltage...
This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements analysis are performed as a function temperature for first time, focusing on cryogenic applications, down to 4.2 K. back bias impact device is evaluated. results reveal that threshold voltage tuning found be independent, allowing extra drain current improvement. particularly interesting short channel devices, whose gain with...
HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -based ferroelectric FETs (FeFETs) offer excellent retention, scalability, and memory window. However, achieving high endurance is still challenging. Here, a fluorination treatment presented that enables significant device stability improvement. Noise charge pumping methods are applied to obtain deeper understanding of the underlying defect interaction in FeFETs.
This article reports an improvement in the performance of hafnium oxide-based (HfO2) ferroelectric field-effect transistors (FeFET) achieved by a synergistic approach interfacial layer (IL) engineering and READ-voltage optimization. FeFET devices with silicon dioxide (SiO2) oxynitride (SiON) as IL were fabricated characterized. Although FeFETs SiO2 interfaces demonstrated better low-frequency characteristics compared to SiON interfaces, latter WRITE endurance retention. Finally, neuromorphic...
This article proposes a memory cell, denoted by 1F-1T, consisting of ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting (T). The reduces the impact drain current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$I_{d}$</tex-math></inline-formula> ) variations limiting on-state in FeFET. experimental data from our 28nm high-k-metal-gate (HKMG) based FeFET calibrates and...
This article reports an improvement in the low- frequency noise characteristics hafnium oxide-based (HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ) ferroelectric field-effect transistors (FeFET) by interfacial layer (IL) engineering. FeFET devices with silicon dioxide (SiO and oxynitride (SiON) as IL were fabricated characterised. FeFETs SiON interfaces demonstrated excellent variation, low-frequency characteristics. The wider...
<p>This letter proposes a memory cell, denoted by 1F-1T, consisting of ferroelectric field-effect transistor (Fe-FET) cascoded with another current-limiting (T). The reduces the impact drain current (Id) variations limiting on-state in FeFET, 1F. We have fabricated 28nm high-k-meta-gate (HKMG) based FeFETs, and experimental data is used to model simulate single-cell arrays. simulation shows significant improvement bit-line (BL) (IBL ) variation for 1F-1T array. Finally, system-level...
We report the observation at low temperature of a hump in linear transfer characteristic thin film fully depleted silicon-on-insulator transistor when positive bias is applied on back gate under buried oxide. This decrease current correlated with transition from one-subband to two-subband conduction. Electron mobility measurements and calculations are good agreement occurrence intersubband scattering carrier transport two-dimensional inversion layer.
In this invited article we present a comprehensive overview of 28 nm high-k-metal gate-based ferroelectric field effect transistor devices for synaptic applications. The under test were fabricated on 300 mm wafers at GlobalFoundries. demonstrate 103 WRITE-endurance cycles and 104 seconds data-retention capability 85 °C. We have also assessed the FeFET-based crossbar array's performance in system-level system was by simulating FeFET array neuromorphic For datasets from National Institute...
This paper presents a detailed investigation of the quasi-static capacitance-voltage (QSCV) technique in pseudo-metal-oxide-semiconductor field effect transistor (pseudo-MOSFET) configuration for evaluating interface quality bare silicon-on-insulator (SOI) wafers, without processing dedicated metal-oxide-semiconductor (MOS) test devices. A physical model is developed that capable explaining experimental results. In addition, frequency effects are used to validate equations by systematic...
We examine in detail the experimental setup for fast, situ characterization of bare SOI substrates using pseudo-MOSFET technique. Two main conditions are analyzed: back contact between wafer and metal chuck, influence probes placement (location pressure) on die surface. Static I-V split-CV measurements reported parameter extraction methods update. focus carrier mobility define pragmatic guidelines simple accurate extraction.
We report an experimental pFET with 420GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , which to the best of our knowledge is highest value reported for a silicon pFET. The transconductance 1800uS/um. technology fully depleted on insulator (FDSOI) channel formed by SiGe condensation. This outstanding performance achieved combination layout and process optimization minimizes capacitance maximizes compressive strain channel....
This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance MOSFET on 22FDX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> . The f <inf xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> can be improved by 50% up to 75% for NFET PFET with respect a standard 2.0µm finger width layout, respectively.
This paper reports that large polarization <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(2\mathrm{P}_{\mathrm{r}}\approx 35.3\ \mu\mathrm{C}/\text{cm}^{2})$</tex> can be demonstrated in Si-doped Hf02 Metal-Ferroelectric-Insulator-Semiconductor Capacitors with proper annealing temperature. In addition, wake-up free characteristic as well good retention for up to 10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> seconds is observed...
Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in pseudo-MOSFET configuration. This paper analyzes capacitance and conductance versus frequency characteristics. We discuss conditions under which it is possible to extract interface trap density bare SOI wafers. The indicate, both simulations, that signature due present small-area samples, but masked by RC response channel regular, large-area...
This work presents the impact of carrier distribution in RTN and LFN performance. Using ad-hoc devices 22nm FDSOI technology, we show how free conduction channel is modulated by applied back-bias as well integrated type. Appropriate use potential n-type leads to minimum device noise overcoming standard bulk technology.
With different device doping options in fully depleted silicon-on-insulator (FDSOI) metaloxide semiconductor field effect transistor (MOSFET) channel and under bias conditions the low frequency noise level can be manipulated optimized. We demonstrated a dependence on lowering of gate input voltage (SVG) with back voltages (Vb) n-type metal-oxide (NMOS) p-type (PMOS) structures.
A major reliability concern in modern high-k field effect transistors (FETs) resembles the defect density distribution within hafnium oxide layer as well its interaction with interfacial layer. For a deeper understanding of charged traps both energetically spatially, it is essential to upgrade from two level charge pumping scheme three scheme. Through variation pulse width and amplitude subsequent second pulse, energy location can be extracted inside gate stack, which important understand...
The paper presents an experimental study aiming to highlight the potential of scanning microwave microscopy (SMM) as a non-destructive high precision characterization tool for SOI technology. Two identical wafers having passivated and non-passivated top Si film surfaces have been assessed. Differential measurements were found capable detecting differences in structures two samples. results support conclusion that, after appropriate calibration method, SMM may provide powerful offering nm scale
This article reports 28 nm high-k-metal-gate (HKMG) based 3bits/cell memory with one ferroelectric (Fe) field effect transistor (FeFET) and reconfigurable resistor (R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). R , connected the select line (SL) drain terminal of FeFET, can be reconfigured via SL terminal. R2 implemented by using a standard metal-oxide-semiconductor (MOSFET) as voltage controlled or any two programmable resistors....
We propose an original Technology/Design Co-optimization of standard cells mixing devices different threshold voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -flavors) within a cell. It is successfully applied with nMOS Low-V (LVT) and pMOS Super-Low-V (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI using diffusion breaks. enables adjusting the V subject to SiGe-channel-induced Local Layout...
An improved set of Scribe Line Monitors (SLMs) with high device densities have been designed for inline monitoring Random Telegraph Noise (RTN) and transistor local mismatch. This infrastructure offers increased statistics from measurement on a single wafer parallel Device Under Test (DUT) testing capability thereby having an efficient time. The characterization results engineering silicon are presented in this paper.