Aggressive memory density scaling causes modern DRAM devices to suffer from RowHammer, a phenomenon where rapidly activating (i.e., hammering) row can cause bit-flips in physically-nearby rows. Recent studies demonstrate that DDR4/LPDDR4 chips, including chips previously marketed as RowHammer-safe, are even more vulnerable RowHammer than older DDR3 chips. Many works show attackers exploit reliably mount system-level attacks escalate privilege and leak private data. Therefore, it is critical...

RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (i.e., hammering) row can cause bit flips in physically nearby rows. The worsens as cell size and cell-to-cell spacing shrink. Recent studies demonstrate that modern chips, including chips previously marketed RowHammer-safe, are even more vulnerable to than older such the required hammer count flip has reduced by 10X last decade. Therefore, it essential develop better understanding in-depth insights into of...

Read mapping is a fundamental step in many genomics applications. It used to identify potential matches and differences between fragments (called reads) of sequenced genome an already known reference genome). costly because it needs perform approximate string matching (ASM) on large amounts data. To address the computational challenges analysis, prior works propose various approaches such as accurate filters that select reads within dataset genomic read set) must undergo expensive...

Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory in modern DRAM chips. For example, RowHammer awell-studied read-disturb phenomenon where repeatedly opening closing (i.e., hammering) a row many times causes bitflips physically nearby rows.

RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and precharging row, thus alternating the voltage of row's wordline between low high levels, can cause bit flips in physically nearby rows. Recent chips are more vulnerable to RowHammer: with technology node scaling, minimum number activate-precharge cycles induce flip reduces error rate increases. Therefore, it critical develop effective scalable approaches protect modern systems against RowHammer. To enable such...

Commodity DRAM-based processing-using-memory (PuM) techniques that are supported by off-the-shelf DRAM chips present an opportunity for alleviating the data movement bottleneck at low cost. However, system integration of these imposes non-trivial challenges yet to be solve d . Potential solutions require appropriate tools develop any necessary hardware and software components. Unfortunately, current proprietary computing systems, specialized DRAM-testing platforms, or simulators do not...

We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used almost all computing systems as main memory. is phenomenon repeatedly accessing a row real chip causes bitflips (i.e., data corruption) physically nearby rows. This leads to serious widespread system security vulnerability, many works since original paper 2014 have shown. Recent analysis reveals problem getting much...

To understand and improve DRAM performance, reliability, security, energy efficiency, prior works study characteristics of commodity chips. Unfortunately, state-of-the-art open source infrastructures capable conducting such studies are obsolete, poorly supported, or difficult to use, their inflexibility limits the types they can conduct. We propose Bender, a new FPGA-based infrastructure that enables experimental on Bender offers three key features at same time. First, directly interfacing...

Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has potential significantly reduce or eliminate costly data movement between processing elements and main memory. A common approach for architectures make use bulk bitwise computation (e.g., AND, OR, NOT). Prior works experimentally demonstrate three-input MAJ (i.e., MAJ3) two-input AND OR operations in commercial...

Read disturbance in modern DRAM chips is a widespread phenomenon and reliably used for breaking memory isolation, fundamental building block robust systems. RowHammer RowPress are two examples of read where repeatedly accessing (hammering) or keeping active (pressing) location induces bitflips other locations. Unfortunately, shrinking technology node size exacerbates over generations. As result, existing defense mechanisms suffer from significant performance energy overheads, limited...

Processing-using-DRAM (PUD) is a processing-in-memory (PIM) approach that uses DRAM array's massive internal parallelism to execute very-wide (e.g., 16,384-262,144-bit-wide) data-parallel operations, in single-instruction multiple-data (SIMD) fashion. However, rows' large and rigid granularity limit the effectiveness applicability of PUD three ways. First, since applications have varying degrees SIMD (which often smaller than row granularity), execution leads underutilization, through-put...

DRAM chips are increasingly more vulnerable to read-disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing rows causes bitflips in nearby due density scaling. Under low thresholds, existing mitigations either incur high area overheads or degrade performance significantly. We propose a new mitigation mechanism, CoMeT, that prevents with area, performance, energy costs DRAM-based systems at very thresholds. The key idea of CoMeT is use low-cost scalable hash-based...

RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) row of cells (DRAM row) induces bitflips physically nearby rows (victim rows). To ensure robust operation, state-of-the-art mitigation mechanisms restore the charge potential victim (i.e., they perform preventive refresh or restoration). With newer chip generations, these more aggressively and cause larger performance, energy, area overheads. Therefore, it essential to develop better understanding...

We 1) present the first rigorous security, performance, energy, and cost analyses of state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting (PRAC) 2) propose Chronus, a new mechanism that addresses PRAC's two major weaknesses. Our analysis shows system performance overhead on benign applications is non-negligible for modern DRAM chips prohibitively large future are more vulnerable to disturbance. identify weaknesses PRAC cause these overheads. First,...

Modern DRAM chips are subject to read disturbance errors. State-of-the-art mitigations rely on accurate and exhaustive characterization of the threshold (RDT) (e.g., number aggressor row activations needed induce first RowHammer or RowPress bitflip) every (of which there millions billions in a modern system) prevent bitflips securely with low overhead. We experimentally demonstrate for time that RDT significantly unpredictably changes over time. call this new phenomenon variable (VRD). Our...

True random number generators (TRNG) sample physical processes to create large amounts of numbers for various use cases, including security-critical cryptographic primitives, scientific simulations, machine learning applications, and even recreational entertainment. Unfortunately, not every computing system is equipped with dedicated TRNG hardware, limiting the application space security guarantees such systems. To open enable overwhelming majority systems that do necessarily have hardware...

DRAM is the building block of modern main memory systems. cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interfering with accesses. As chip density increases technology node scaling, refresh also increase be-cause: 1) number rows in a increases; and 2) need additional mitigate bit failures caused RowHammer, failure mechanism that becomes worse scaling. Thus, it critical enable at low overhead. To this end, we propose new operation,...

Modern computing systems access data in main memory at coarse granularity (e.g., 512-bit cache block granularity). Coarse-grained leads to wasted energy because the system does not use all individually accessed small portions words , each of which typically is 64 bits) a block. In modern DRAM-based systems, two key coarse-grained mechanisms lead energy: large and fixed-size (i) transfers between DRAM controller (ii) row activations. We propose Sectored DRAM, new, low-overhead substrate that...

Long-latency load requests continue to limit the performance of modern high-performance processors. To increase latency tolerance a processor, architects have primarily relied on two key techniques: sophisticated data prefetchers and large on-chip caches. In this work, we show that: (1) even state-of-the-art prefetcher can only predict half off-chip average across wide range workloads, (2) due increasing size complexity caches, fraction an request is spent accessing cache hierarchy solely...

RowHammer (RH) is a significant and worsening security, safety, reliability issue of modern DRAM chips that can be exploited to break memory isolation. Therefore, it important understand real chips' RH characteristics. Unfortunately, no prior work extensively studies the vulnerability 3D-stacked high-bandwidth (HBM) chips, which are commonly used in GPUs.In this work, we experimentally characterize HBM2 chip. We show 1) different channels exhibit significantly levels (up 79 % difference bit...