A5114376231- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Structural Load-Bearing Analysis
- Ferroelectric and Negative Capacitance Devices
- Ion-surface interactions and analysis
- Thin-Film Transistor Technologies
- Structural Behavior of Reinforced Concrete
- HVDC Systems and Fault Protection
- Hydrogen embrittlement and corrosion behaviors in metals
- Silicon Carbide Semiconductor Technologies
- Structural Engineering and Vibration Analysis
- Silicon and Solar Cell Technologies
- 3D IC and TSV technologies
- Non-Destructive Testing Techniques
- High-Voltage Power Transmission Systems
- GaN-based semiconductor devices and materials
- Advanced materials and composites
- Erosion and Abrasive Machining
- Nanowire Synthesis and Applications
- Powder Metallurgy Techniques and Materials
- Low-power high-performance VLSI design
- Protein Structure and Dynamics
- Corrosion Behavior and Inhibition
- VLSI and Analog Circuit Testing
Soitec (France)
2020-2022
Kongju National University
2015-2021
Jeonbuk National University
2017
Soongsil University
2017
Samsung (South Korea)
2001-2011
Chungbuk National University
2010
Korea Basic Science Institute
2010
Integrated Device Technology (United States)
2007
Micron (United States)
2007
Matériaux Ingénierie et Science
2006
In the transition layer of Si(001)–SiO2 interface, Si lattice strain and its distribution were directly observed by medium energy ion scattering spectroscopy for thermal beam oxides. The was in vertical direction, maximum values at SiO2 side 0.96% 2.8% oxides, respectively.
LEG (Laser-induced Epitaxial Growth) process has been proposed to obtain the single c-Si layer over oxide and successfully demonstrated with cell-stacked high density SRAM. With process, energy of laser beam seed formation are key factors determine crystal quality Si on oxide. CMOSFETs film prepared by have excellent behaviors in terms both performance its variations. It is found that SRAMs stacked cell transistor fully worked lowest stand-by current less than 0.3uA/Mb date. believed be a...
Densification during liquid‐phase sintering of WC–Co with various WC powder sizes has been measured in order to identify the densification mechanism. During heating compacts solid state, was enhanced a reduction size. However, behavior reversed when occurred presence liquid: increasing This result is contradiction prediction conventional theory sintering, contact flattening theory, but good agreement pore‐filling theory. Microstructural analysis further confirmed that at temperature by pore...
In this paper, we proposed a series-connection-type superconducting fault current limiter (SFCL) that can prevent the internal magnetic flux generation of cores during normal operation and saturation due to sudden at initial stage occurrence while limiting peak current. The SFCL does not mediate two cores, as previously reported, but mediates single E-I core having configuration magnetically coupled circuits using first, second, third windings. other path is formed by coil element isolated...
In this paper, the fault current limiting (FCL) characteristics of a flux-coupled type superconducting limiter (SFCL) with parallel connection between two windings in DC system were analyzed. The SFCL was composed coils connected and element (SE), which series secondary coil. works systems similar to those AC systems. Before occurs, respective magnetic fluxes generated by offset each other, maintaining voltage induced at zero. case fault, however, resistance is SE, preventing from offsetting...
A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total especially including gate-induced drain (GIDL) component, B-T found to be more sensitive than widely-used gate-oxide degradation Fowler-Nordheim (F-N) tunneling stress. bias also gives significantly higher stress-induced (SILC)...
For the first time, a highly manufacturable fin-channel array transistor (FCAT) on bulk Si substrate has been successfully integrated in 512 M density DRAM with sub-70nm technology. The FCAT shows an excellent short channel behavior, such as extremely low subthreshold swing (SS) (/spl sim/75mV/dec) and DIBL sim/13mV/V), high cell drive current remarkably leakage sim/0.2fA/cell).
The effects of TaN metal-gate thickness on the electrical characteristics poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin was reactive with poly-Si gate, which led to formation Si-doped metal gate. As a result, work function gate reduced and capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN channel engineering strained-Si substrate showed threshold voltage - 0.45 V at W/L= 10/1 /spl mu/m improved MOSFET characteristics.
We proposed and successfully demonstrated partially insulated bulk MOSFETs with multiple V/sub th/s, I/sub on/s, Off/s by using partial SOI process without complex wafer. Both nMOS pMOS applicable to the HP LSTP transistors were simultaneously implemented on same wafer except process. These results must be very useful implement IC systems requiring various specifications of TH/s, On/s, Off/s.
In this paper, the dual peak current limiting characteristics of superconducting fault limiters (SFCLs) using iron cores were compared to each other. The SFCLs connected in series between two coils (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> and N xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). However, differently source location. power burden these could be varied depending on design factors, such as location coils. Using...
The paper presents shear lag parameters for beam-to-column connections in steel box piers. Previous researches have analyzed piers using a parameter <TEX>${\eta}_o$</TEX> obtained from simple beam model, which is not based on reasonable design assumption. Instead, the current proposes cantilever model and has proved effectiveness through theoretical experimental studies. examines inaccuracy of previous by estimating effective width, width-span length ratio L/b, sectional area S beam. Two...
An understanding of the folding states α-helical membrane proteins in detergent systems is important for functional and structural studies these proteins. Here, we present a rapid simple method identification topology assembly transmembrane helices using paramagnetic perturbation nuclear magnetic resonance spectroscopy. By monitoring signals from glycine residues located at specific sites, were easily identified without time-consuming backbone assignment. This validated with Mistic...
A functional DRAM with higher data retention characteristics than a planar access device has been demonstrated, using metal gate recessed (RAD). Chemical vapor deposition (CVD) and atomic layer (ALD) were used to deposit titanium nitride (TiN) tantalum (TaN), respectively. CVD TiN ALD TaN-CVD laminate stacks integrated RAD module. gates showed enhanced drive current (IDS), transconductance (GM), mobility (μEFF) reduced off (IOFF) compared gates. Device reliability for both the devices RADs...
The band-to-defect tunneling (BDT) induced junction leakage current of high density DRAM cell transistors under off-state bias-temperature (B-T) stress was studied in detail for the first time. It found that BDT is most critical limiting transistor scaling. new B-T proven to be a very effective reliability assessment tool degradation transistor. also useful assessing future DRAMs.
Although cyclic AMP receptor protein ( CRP ) has long served as a typical example of effector‐mediated allostery, mechanistic details into its regulation have been controversial due to discrepancy between the known crystal structure and NMR apo‐ . Here, we report that recombinant corresponding C‐terminal DNA ‐binding domain CDD forms dimer. This result, together with structural information obtained in present study, is consistent previous validates relevance also solution. Therefore, our...
The SiGe SD structure in peripheral PMOS area of DRAM was successfully integrated without any degradation NMOS properties, which is the first approach to DRAM. performance enhancement found be more than 40%. authors suggest as key solution for improvement transistor properties sub-50nm technology
AbstractAbstractThe contributions of anodic and cathodic reactions to the acoustic emission recorded during crevice corrosion 304L austenitic stainless steel have been investigated. During experiments, propagation was localised on an sample, whereas were isolated a separate specimen. The application shot-peening and/or sample surfaces allowed control over distribution both specimens. treatment led increased rate, due increase in current density. It has established that most energetic...
We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si substrate, named Partially-insulated-RCAT (Pi-RCAT) to suppress body effect of conventional and improve current drivability DRAM cell. The Pi-RCAT demonstrated superior characteristics effect, subthreshold slope (SW) higher with comparable I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...