Integrated voltage regulators (IVRs) are one of the main trends in power delivery networks (PDNs) for electronic systems. A major challenge IVR design is to achieve sufficient integration / minimization required passive components while still maintaining high efficiency. This paper demonstrates that a buck converter type designed with package embedded magnetic core inductors can very efficiency substantially reduced area requirement compared "air core" inductors. For final design, an...

Complex SoCs in scaled CMOS processes integrate a large variety of digital, SRAM and noise-sensitive mixed-signal/analog circuit blocks such as PLLs, wireline/wireless/RF transceivers, sensor front-ends, etc. The on-die low-dropout regulators (LDO) used for fine-grain DVFS digital memory must respond fast to load transients minimize voltage droops/overshoots without using decoupling caps, while minimizing power overheads over wide operating range. analog circuits, on the other hand, need...

A variation-adaptive computational digital low dropout (CDLDO) regulator featuring an event-driven controller (CC) is presented, which computes the required number of power gates (PGs) unlike traditional IIR filter-based control techniques to regulate output voltage for any load/reference transient. The CC ensures ~ns transient response with a deterministic two-event duration settling time, independent dynamic range load or capacitor value. Measurement results 10-bit PG design demonstrate...

An inductive boost regulator is presented that can harvest energy over a wide input voltage range. The range enabled by current-based analog oscillator capable of providing very high duty cycle. control circuits are designed to operate at subthreshold enable low all electronic autonomous startup. A test chip in 130-nm CMOS demonstrates harvesting from as 12-mV while biased an external 1-V battery and (without using any additional device or battery) startup above 305 mV output. design...

Fully integrated voltage regulators (FIVRs) offer many advantages, such as fine-grained power management, fast transient response, and reduced form factor. This article addresses light-load efficiency in FIVRs with nH-scale air-core inductors. The challenges of implementing efficient discontinuous conduction mode (DCM) operation at high switching frequencies are discussed, which include zero current detection, inductor ac-loss effects, delivery network (PDN) resonances. A prototype 14-nm...

Negative gate transconductance (NGT) is shown in gate/source overlapped heterojunction tunnel FET (SO-HTFET). At higher VGS, depletion region the source reduces electric field along channel resulting reduced band-to-band-tunneling and NGT. Application of SO-HTFET designing a single transistor binary phase shift-keying with significantly complexity discussed.

This paper presents a novel idea of vehicle tracking system based on the existing GSM cellular networks. A software is proposed that sends specialized request to networks call any particular ID. The ID actually SIM kept in special kit inside capable receiving phone automatically. As soon as established, cell information available BSC which then passed software. Based collected, will initiate forced handover another suitable and receive too. Upon completion two consecutive handovers, i.e.,...

This article presents a universal modular hybrid low-dropout regulator (MHLDO) to provide any desired combination of the power supply rejection ratio (PSRR) and conversion efficiency (PCE) with in-compliance output ripple, load transient response, operating range while minimizing losses decoupling capacitor. The architecture eliminates need for fine quantization digital LDO gates prevents associated limit cycle oscillation keeping overheads low. It is configurable at design-time robustly...

As the supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) approaches device threshold xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), elevated temperature results in increased current. This phenomenon is generally known as Inverse Temperature Dependence (ITD). In this paper, we propose a test structure with built-in poly-resistor-based heater to characterize ITD digital circuits. Our measurements from 130nm...

This paper presents a single-chip image sensor node with energy harvesting from the pixel array. The design includes 128 × 96 array that can be reconfigured to form an on-chip photovoltaic cell harvest energy. An onchip power management unit harvests array, and delivers multiple regulated output voltage domains sensor, processor, memory. processor is low-overhead moving object detection reduce volume of transmitted data. proposed implemented on single die in 130-nm technology. demonstrates...

Self-powered wireless sensors require power delivery systems capable of harvesting from very low input voltage while consuming minimal bias current. This paper presents a multistage boost regulator generating 3 V to supply RF blocks in self-powered 10 mV voltage. The consumption is minimized using automated gating. efficiency the conversion at high ratio enhanced through regulation and control intermediate-node A test chip, fabricated 130 nm CMOS, demonstrates functional operation as...

This paper demonstrates a new approach to model the impact of thermal effects on efficiency integrated voltage regulators (IVRs) by combining analytical evaluations with coupled electrical and simulations. An application shows that system-in-package solution avoids problems typically observed in other IVR designs. While evaluation this focuses loss inductor wiring PDN, developed is general enough also impacts power dissipation cores buck converter chip.

This paper presents a CMOS circuit, designed for smoothing out the inrush current of DC-DC boost regulator. A current-on-capacitor based clamped reference is along with common source amplifier and high speed comparator. The linearly varying using MOSFET connected in diode configuration, ensuring smooth transition from ramp mode to normal mode, which unique feature this proposed circuit. input inductor sensed small resistance at NMOS power transistor producing sense voltage. voltage then...

High-performance many-core processors and GPUs demand 100s of Watts power in a single voltage/power domain on chip, operating below 1V. High-frequency highcurrent-density fully integrated voltage regulators (FIVRs) with in-package air core inductors (ACIs) [1] or on-package magnetic can deliver high efficiency low distribution losses compact footprints. Multiple FIVR tiles must be "ganged" to support the large on-chip domains while meeting reliability constraints active passive elements,...

A mathematical analysis of efficiency optimization for PFM (pulse frequency modulation) mode boost regulator has been presented in this paper. Based on the load demand, input voltage and output a booster can operate single pulse or multi operation. The reveals relationship between operating operation considering external internal parameters which loss occurs. This paper also presents maximum delivering capacity inductor size where separate modes are distinguished.

An autonomously bias gated synchronous boost regulator consuming 110nA at 1V is demonstrated in 130nm CMOS. The IC generates regulated output from 30mV input, starts up (battery-less) 265mV, and regulates ranging 0.78V-3.3V. peak efficiency 83% with 10μA 85% 10mA load.

This paper presents an on-chip thermoelectric (TE) energy management system for energy-efficient on-demand active cooling of integrated circuits. Embedding a TE module (TEM) within the package has shown potential circuits (ICs); however, additional limits effectiveness coolers (TEC). The proposed monitors IC temperature and provides during critical thermal events by operating TEM in Peltier mode. During normal operation, is operated Seebeck mode to harvest otherwise wasted heat generated...

This paper proposes a simple technique to measure the Equivalent Series Resistance (ESR) of capacitor. method uses switching DC-DC boost regulator ESR. is very in technique, consumes little time and requires only instruments.

Thermoelectric (TE) devices have shown promise for on-demand cooling of ICs. However, the additional energy required remains a challenge successful deployment these devices. This paper presents closed loop control system that dynamically switches TE module between Peltier and Seebeck modes depending on chip temperature. The autonomous harvests during regular operation uses harvested to cool high power operation. is demonstrated using commercial thin-film device, an integrated boost regulator...

This paper presents an on-chip digitally programmable test structure, referred to as the field thermal emulator (FPTE), for on-line characterization of power pattern, time-varying field, and associated changes in electrical characteristics transistors. A chip was designed 130nm CMOS validate structure. The measurement results demonstrated ability FPTE emulate various patterns capture effects on temperature circuit performance.

Distributed small-scale electronics for IoT applications are on the rise. Power delivery such requires innovative design techniques to improve energy efficiency. This paper summarizes challenges devices and discusses several efficient power units. Such solutions cover like harvesting from very low input voltage, maximized harvesting, with multiple voltage domains using sustain higher than breakdown voltages.

Thermal system identification (TSI) is presented as a methodology to characterize and estimate the transient thermal field of packaged IC for various workloads considering chip-to-chip variations in electrical properties. The time-frequency duality used identify low-pass filter frequency domain through on-line power/thermal measurements on IC. identified characteristic an individual prediction that specific power pattern. A test-chip, fabricated 130-nm CMOS, demonstrates effectiveness TSI...

This paper presents a circuit implementation to fulfill the demand of non-linear slope compensation improve stability in switching peak current mode DC-DC boost converter. The is implemented by regular threshold voltage NMOS and PMOS standard on-chip pico-Farad range capacitor biased PTAT current. Using quadratic nature drain MOS device saturation generates compensating signal on cycle basis this added with sense compensate disturbance that might arise. Along another fixed noise creates...

This paper presents a voltage regulator topology, implemented using low-voltage devices, for converting high input (>4.5 V) to low output voltages with fine-grain control (0.3 1 V). The topology merges Dickson's switched-capacitor stage current-mode inductive buck stage, and optimizes the frequency of operations reduce overall passive size. proposed two-stage hybrid regulator, designed in 130-nm standard digital process, operates from 4.8 6 V at regulates as 0.3 maximum power 90 mW peak...