A5061466560- Cryptographic Implementations and Security
- Physical Unclonable Functions (PUFs) and Hardware Security
- Low-power high-performance VLSI design
- Chaos-based Image/Signal Encryption
- Advanced Memory and Neural Computing
- Security and Verification in Computing
- Semiconductor materials and devices
- Advanced Malware Detection Techniques
- Parallel Computing and Optimization Techniques
- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Advanced DC-DC Converters
- VLSI and Analog Circuit Testing
- Ferroelectric and Negative Capacitance Devices
- Advanced Neural Network Applications
- Innovative Energy Harvesting Technologies
- Silicon Carbide Semiconductor Technologies
- Interconnection Networks and Systems
- CCD and CMOS Imaging Sensors
- Supercapacitor Materials and Fabrication
- Quantum-Dot Cellular Automata
- Coding theory and cryptography
- Digital Media Forensic Detection
- Advanced Battery Technologies Research
- Network Security and Intrusion Detection
IBM Research - Thomas J. Watson Research Center
2020-2024
IBM (United States)
2021-2024
Georgia Institute of Technology
2014-2021
Intel (United States)
2018-2020
Indian Institute of Technology Kharagpur
2013
University of Allahabad
1974
Low-precision computation is the key enabling factor to achieve high compute densities (T0PS/W and T0PS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) in AI hardware accelerators across cloud edge platforms. However, robust deep learning (DL) model accuracy equivalent high-precision must be maintained. Improvements bandwidth, architecture, power management are also required harness benefit of reduced precision by feeding supporting...
This paper demonstrates the improved power and electromagnetic (EM) side-channel attack (SCA) resistance of 128-bit Advanced Encryption Standard (AES) engines in 130-nm CMOS using random fast voltage dithering (RFVD) enabled by integrated regulator (IVR) with bond-wire inductors an on-chip all-digital clock modulation (ADCM) circuit. RFVD scheme transforms current signatures variations AES input supply while adding shifts edges presence global local noises. The measured at node show upto 37×...
Power side-channel attacks (PSCA), e.g. Differential Analysis (DPA) and Correlation (CPA), are major threats to the security of crypto engines in SoC platforms. Circuit-level SCA countermeasures achieve data-independent supply current patterns via implementation using non-conventional logic (complemented or charge recovery) local switched-capacitor-based equalization have been demonstrated. The feasibility bandwidth-limited integrated low dropout regulators, multi-phase switched-capacitor...
This paper demonstrates an integrated inductive voltage regulator (IVR) for improving power side-channel-attack (PSCA) resistance of 128-bit Advanced Encryption Standard (AES-128) engines. An IVR is shown to transform the current signatures generated by encryption engine. Furthermore, all-digital circuit block, referred as loop-randomizer, introduced randomize transformations. A 130-nm test-chip with 11.6-nH inductance, 3.2-nF capacitance, and 125-MHz switching frequency used drive two...
The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use hardware accelerators in their execution. Scaling the performance AI across generations is pivotal success commercial deployments. intrinsic error-resilient nature present a unique opportunity for performance/energy improvement through precision scaling. Motivated by recent algorithmic advances scaling inference training, we designed RaPiD <sup...
Side channel attacks (SCA) exploit data-dependent information leakage through power consumption and electromagnetic (EM) emissions from cryptographic engines to uncover secret keys. Integrated inductive voltage regulators (IVR) with a randomized control loop [1] or switching frequency [2], random dithering [3] have demonstrated improved side-channel analysis (PSCA) resistance. Simulation studies shown PSCA resistance via shunt linear [4]. This paper demonstrates EM SCA of standard...
Design of ultralightweight but secure encryption engine is a key challenge for Internet-of-Things edge devices. This paper explores the system level design space an ultralow power image sensor node communication and proposes optimized datapath architecture 128-bit SIMON (SIMON128), lightweight block cipher, minimal performance, power, area overheads with increased side-channel security. Various architectures are explored simultaneously increasing energy-efficiency resistance to power-based...
This article demonstrates enhanced power (P) and electromagnetic (EM) side-channel analysis (SCA) attack resistance of standard (unprotected) 128-bit advanced encryption (AES) engines with parallel (P-AES, 128-bit) serial (S-AES, 8-bit) datapaths a SIMON engine the bit-serial (1-bit) datapath by an on-die security-aware all-digital low-dropout (DLDO) regulator. The proposed DLDO improves SCA using control-loop-induced perturbations in nominal DLDO, random switching noise injector (SNI)...
A 125-MHz fully integrated inductive buck voltage regulator using 11.6-nH wirebond inductance and 3.2-nF on-chip capacitance is presented in 130-nm CMOS. An all-digital architecture to ease integration digital process nodes. The IVR demonstrates enhanced bandwidth enabled by a multi-sampled compensator with reduced precision computation. fast lightweight auto-tuning engine optimize steady-state stability transient response under variation passives. resistive assist scheme an adaptive...
A 10nm digital Binary Neural Network (BNN) chip implements 1b activations and weights for compute density of 418TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> memory 414KB/mm . The achieves an energy efficiency 617TOPS/W by leveraging Compute Near Memory (CNM), parallel inner product compute, Near-Threshold Voltage (NTV) operation. BNN design approaches the analog in-memory techniques while also ensuring deterministic, scalable, precise
A binary neural network (BNN) chip explores the limits of energy efficiency and computational density for an all-digital deep (DNN) inference accelerator. The intersperses data storage computation using near memory (CNM) to reduce interconnect movement costs. It performs wide inner product operations leverage parallelism inherent in DNN computations. BNN leverages lightweight pipelining at a near-threshold voltage (NTV) overhead sequential elements. employs optimized access patterns accesses...
The power attack protection of encryption engines often comes at the expense area, power, and/or performance overheads making design a low-power and compact but secure engine challenging. This paper explores feasibility using an on-chip low dropout regulator (LDO) as countermeasure to engine. We area minimized implementation Advanced Encryption Standard (AES) predictive 45nm node show that lightweight implementations are more susceptible attack. Using behavioral modeling, we LDO can enhance...
This paper explores fully integrated inductive voltage regulators (FIVR) as a technique to improve the side channel resistance of encryption engines. We propose security aware design modes for low passive FIVR robustness an encryption-engine against statistical power attacks in time and frequency domain. A Correlation Power Analysis is used attack 128-bit AES engine synthesized 130nm CMOS. The original requires ~250 Measurements Disclose (MTD) 1st byte key; but with security-aware FIVR, CPA...
Enabling data security from unauthorized access is a major challenge for electronics devices. Most of the conventional cryptographic techniques store "keys" in nonvolatile memory, which vulnerable to external attacks like physical attacks, side-channel fault etc. Physically unclonable functions (PUFs) have potential overcome these challenges because they do not keys permanently and are difficult reproduce. The next generation electronic opto-electronic devices may use semiconducting...
Low-drop-out (LDO) voltage regulator modules are being increasingly integrated in the modern processors for efficient power management. This paper shows that an All-Digital LDO (ADLDO) can also be used as a countermeasure against measurement based side channel attacks. The current transformation introduced by digital LDOs, coupled with noise due to quantization and limited sampling rate control loop, helps suppress leakage. ADLDO-based is analyzed considering Advanced Encryption Standard...
The proliferation of ubiquitous computing requires energy-efficient as well secure operation modern processors. Side channel attacks are becoming a critical threat to security and privacy devices embedded in infrastructures. Unintended information leakage via physical signatures such power consumption, electromagnetic emission (EM) execution time have emerged key consideration for SoCs. Also, published on purpose at user privilege level accessible through software interfaces results...
Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precisions—FP16, Hybrid-FP8 (HFP8), INT4, and INT2—to support diverse application demands training inference. The leverages cutting-edge algorithmic advances to demonstrate leading-edge power efficiency 8-bit floating-point (FP8) INT4 inference without...
This article demonstrates all-digital tuning and dynamic control of feedback compensator in digital low drop out regulators to enhance the transient performance under process passive variations, aging, load changes. The measured results from a 130-nm CMOS test-chip shows 2.1× improvement variations 30% for aging-induced degradations. We demonstrate 55-ns setting time 5 45 mA step 100 ps, with 97.8% peak current efficiency.
Cryptographic circuits such as advanced encryption standard (AES) are vulnerable to correlation power analysis (CPA) side-channel attacks (SCAs), where an adversary monitors chip supply current signatures or electromagnetic (EM) emissions decipher the value of embedded keys. This article describes all-digital, fully synthesizable SCA-resistant 16-b serial AES-128 hardware accelerator fabricated in 14-nm CMOS, occupying 4900 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
The paper demonstrates improved power side channel attack (PSCA) resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive regulator (IVR) and all-digital clock modulation (ADCM). measured signatures at IVR supply nodes show 9× reduction peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation analysis (CPA) attacks even after 500,000 traces.
This paper shows that inductive integrated voltage regulators (IVR) provide significant immunity to traditional power attacks on crypto encryption engines based timedomain analysis of the chip current. Frequency-domain analyses envelope and duty cycle current are identified as new attack modes. The security-aware IVR design is discussed additional attack.
This paper analyzes the effect of variations in parameters an Integrated Voltage Regulator (IVR) and its impact on power/performance a system IVR driven digital logic circuit. The coupled analysis considering integrated passives, power train FETs controller transistors shows, compared to off-chip VR, induce much larger shifts operating frequency total power. Variations output filter passives cause most prominent performance, particularly pronounced at low voltage operation core. We also show...
The shift in paradigm from cloud computing toward edge has resulted faster response times, a more secure and energy-efficient edge. Internet-of-Things (IoT) devices form vital part of the edge, but despite legions benefits it offers, increasing vulnerabilities escalation malware generation rendered them insecure. Software-based approaches are prominent detection, they fail to meet requirements for IoT devices. Dynamic power management (DPM) is architecture agnostic inherently pervasive...
The rapid emergence of AI models, specifically large language models (LLMs) requiring amounts compute, drives the need for dedicated inference hardware. During deployment, compute utilization (and thus power consumption) can vary significantly across layers an model, number tokens, precision, and batch size [1]. Such wide variation, which may occur at fast time scales, poses unique challenges in optimizing performance within system-level specifications discrete accelerator cards, including...
This paper demonstrates a new approach to model the impact of thermal effects on efficiency integrated voltage regulators (IVRs) by combining analytical evaluations with coupled electrical and simulations. An application shows that system-in-package solution avoids problems typically observed in other IVR designs. While evaluation this focuses loss inductor wiring PDN, developed is general enough also impacts power dissipation cores buck converter chip.