A5007389870- Real-Time Systems Scheduling
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Distributed systems and fault tolerance
- Interconnection Networks and Systems
- Distributed and Parallel Computing Systems
- Cloud Computing and Resource Management
- Advanced Data Storage Technologies
- Software System Performance and Reliability
- Advanced Software Engineering Methodologies
- Scheduling and Optimization Algorithms
- Petri Nets in System Modeling
- Real-time simulation and control systems
- Software Reliability and Analysis Research
- Simulation Techniques and Applications
- Formal Methods in Verification
- Advanced Control Systems Optimization
- Healthcare Technology and Patient Monitoring
- Low-power high-performance VLSI design
- Safety Systems Engineering in Autonomy
- Process Optimization and Integration
- Software Engineering Research
- Neural Networks and Applications
- Context-Aware Activity Recognition Systems
- Optical Systems and Laser Technology
Institut Polytechnique de Bordeaux
2012-2024
Université Toulouse III - Paul Sabatier
2013-2024
Travaux et Recherches Archéologiques sur les Cultures, les Espaces et les Sociétés
2002-2024
Université Toulouse-I-Capitole
2012-2024
Institut de Recherche en Informatique de Toulouse
2012-2024
Centre National de la Recherche Scientifique
2005-2024
Université Toulouse - Jean Jaurès
2012-2024
Université de Toulouse
2008-2015
University of Augsburg
2010
Centre de Recherche en Informatique
2000
The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support system software, and worst-case execution time analysis tools for embedded multicore processors. focuses on developing processor designs systems techniques guarantee the analyzability timing predictability of every feature provided by processor.
A large class of embedded systems is distinguished from general-purpose computing by the need to satisfy strict requirements on timing, often under constraints available resources. Predictable system design concerned with challenge building for which timing can be guaranteed a priori . Perhaps paradoxically, this problem has become more difficult introduction performance-enhancing architectural elements, such as caches, pipelines, and multithreading, introduce degree uncertainty make...
Engineering related research, such as research on worst-case execution time, uses experimentation to evaluate ideas. For these experiments we need example programs. Furthermore, make the repeatable those programs shall be made publicly available. We collected open-source programs, adapted them a common coding style, and provide collection in open-source. The benchmark is called TACLeBench available from GitHub version 1.9 at publication date of this paper. One main features that all are...
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in is expected by parallelizing applications and running them on an multi-core processor, which enables combining requirements high-performance with timing-predictable execution. parMERASA will provide timing analyzable system of parallel scalable multicore processor. goes one step beyond mixed criticality demands: It...
When integrating mixed critical systems on a multi/many-core, one challenge is to ensure predictability for high criticality tasks and an increased utilization low tasks. In this paper, we address problem when several with different deadlines, periods offsets are concurrently executed the system. We propose distributed run-time WCET controller that works as follows: (1) locally, each task regularly checks if interferences due can be tolerated, otherwise it decides their suspension; (2)...
To meet performance requirements as well constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question of timing analysability is raised these architectures. In MERASA project, a WCET-aware multicore processor has been appropriate system software. They both guarantee that WCET tasks running dierent cores can safely analyzed since their possible interactions bounded. Nevertheless, computing parallel application still not...
Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general embedded computing domains. However, currently available multi-cores not feasible be used safety-critical environments with hard real-time constraints. Hard tasks running on different cores must executed isolation or their interferences time-bounded. Thus, new requirements also arise for a operating system (RTOS), particular if parallel execution of applications should supported. In this...
Although multi/many-core platforms enable the parallel execution of tasks, sharing resources may lead to long WCETs that fail meet real-time constraints system. Then, a safe solution is most critical tasks in isolation followed by remaining tasks. To improve system performance, we propose an approach where task can run with less as are met. When no further interferences be tolerated, proposed run-time control suspends low until termination task. In this paper, describe design and prove...
The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential program transformation based design patterns that are timing analyzable. applied parallelize the following industrial programs: 3D path planning and stereo navigation algorithms (Honeywell...
Multi-core architectures are being increasingly used in embedded systems as they offer several advantages: improved hardware integration, low thermal dissipation and reduced energy consumption, while make it possible to improve the computing power. In order run real-time software on a multicore architecture, Worst-Case Execution Time of every thread should be achievable. This notably involves bounding memory latencies by employing predictable bus arbiter. However, state-of-the-art techniques...
The wider and use of high-performance processors as part real-time systems makes it more difficult to guarantee that programs will respect their strict deadlines. While the computation worst-case execution times (WCET) relies on static analysis code, challenge is model, with enough safety accuracy, behaviour intrinsically dynamic components. We focus branch predictor. Several models bound number mispredictions have previously been published. Some them exhibit a high complexity while others...
The time predictability of the components a real-time system is required whenever it must be guaranteed that deadlines will met. Research on techniques to evaluate Worst-Case Execution Time (WCET) programs has received much attention these last years but current high-performance processors prove hard model both safely and tightly. We acknowledge difficulty taking into account more dynamic mechanisms within static analysis this motivates our approach consists in making processor fit WCET...
In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software can be implemented in a time analysable way based the proposed hardware primitives. choose to implement primitives memory controller two reasons. Firstly, remove pessimism WCET analysis HRT applications. Secondly, enable that implementation is mostly independent chosen instruction set architecture...
In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software can be implemented in a time analysable way based the proposed hardware primitives. choose to implement primitives memory controller two reasons. Firstly, remove pessimism WCET analysis HRT applications. Secondly, enable that implementation is mostly independent chosen instruction set architecture...
In order to meet performance/low energy/integration requirements, parallel architectures (multithreaded cores and multi-cores) are more considered in the design of embedded systems running critical software. The objective is run several applications concurrently. When have strict real-time constraints, two questions arise: a) how can worst-case execution time (WCET) each application be computed while concurrent might interfere? b)~how tasks scheduled so that they guarantee their deadlines?...
Real-time and time-constrained applications programmed on many-core systems can suffer from unmet timing constraints even with correct-by-construction schedules. Such unexpected results are usually caused by unaccounted for delays due to resource sharing (e.g. the communication medium). In this paper we address three main sources of unpredictable behaviors: First, propose use a deterministic Model Computation (MoC), more specifically, well-formed CSDF subset process networks; Second,...
We present MINOTAuR, a timing predictable open source RISC-V core based on the Ariane [28]. first modify in order to make it following approach used design SIC processor [12]. prove that instruction parallelism does not prevent from enforcing predictability. further relax restrictions by enabling limited amount of speculative execution and we are still able formally is predictable. Experimental results show performance reduced only 10% average compared original core.