A5084795370- Parallel Computing and Optimization Techniques
- Real-Time Systems Scheduling
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Distributed and Parallel Computing Systems
- Distributed systems and fault tolerance
- Advanced Data Storage Technologies
- Advanced Memory and Neural Computing
- Real-time simulation and control systems
- Cloud Computing and Resource Management
- Formal Methods in Verification
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
- Numerical Methods and Algorithms
- Software Reliability and Analysis Research
- Software System Performance and Reliability
- Software Testing and Debugging Techniques
- Scheduling and Optimization Algorithms
- Advanced Data Processing Techniques
- Engineering and Test Systems
- Fault Detection and Control Systems
- Advanced Control Systems Optimization
- Algorithms and Data Compression
- Robotics and Automated Systems
- Simulation Techniques and Applications
Centre National de la Recherche Scientifique
2005-2023
Université Toulouse-I-Capitole
2007-2023
Institut Polytechnique de Bordeaux
2007-2023
Institut de Recherche en Informatique de Toulouse
2008-2023
Université Toulouse - Jean Jaurès
2007-2023
Université Toulouse III - Paul Sabatier
2008-2023
Travaux et Recherches Archéologiques sur les Cultures, les Espaces et les Sociétés
2002-2023
Université de Toulouse
2007-2012
The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support system software, and worst-case execution time analysis tools for embedded multicore processors. focuses on developing processor designs systems techniques guarantee the analyzability timing predictability of every feature provided by processor.
A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents novel cost-effective mechanism called the two-block ahead branch predictor. Information from current instruction block not used for predicting address of next block, but rather following block.This approach overcomes fetch bottle-neck exhibited by wide-dispatch "brainiac" processors enabling them to efficiently predict addresses two blocks...
This paper presents PapaBench, a free real-time benchmark and compares it with the existing suites. It is designed to be valuable for experimental works in WCET computation may also useful scheduling analysis. bench based on Paparazzi project that represents application, developed embedded different Unmanned Aerial Vehicles (UAV). In this paper, we explain transformation process of applied obtain PapaBench. We provide high level AADL model, which reflects behaviors each component system...
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in is expected by parallelizing applications and running them on an multi-core processor, which enables combining requirements high-performance with timing-predictable execution. parMERASA will provide timing analyzable system of parallel scalable multicore processor. goes one step beyond mixed criticality demands: It...
To meet performance requirements as well constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question of timing analysability is raised these architectures. In MERASA project, a WCET-aware multicore processor has been appropriate system software. They both guarantee that WCET tasks running dierent cores can safely analyzed since their possible interactions bounded. Nevertheless, computing parallel application still not...
Many-core processors offer massively parallel computation power representing a good opportunity for the design of highly integrated avionics systems. Such designs must face several challenges among which 1) temporal isolation be ensured between applications and 2) bounds WCET computed real-time safety critical applications. In order to partially address those issues, we propose an appropriate execution model, that restricts behaviours, has been implemented on Kalray MPPA-256. We tested...
Many-core processors are interesting candidates for the design of modern avionics computers. Indeed, computational power offered by such platforms opens new horizons to more demanding systems and integrate applications on a single target. However, they also bring challenging research topics because their lack predictability programming complexity. In this paper, we focus problem mapping large complex platform as KALRAY MPPA®-256 while maintaining strong temporal isolation from co-running...
Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general embedded computing domains. However, currently available multi-cores not feasible be used safety-critical environments with hard real-time constraints. Hard tasks running on different cores must executed isolation or their interferences time-bounded. Thus, new requirements also arise for a operating system (RTOS), particular if parallel execution of applications should supported. In this...
The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential program transformation based design patterns that are timing analyzable. applied parallelize the following industrial programs: 3D path planning and stereo navigation algorithms (Honeywell...
Multi-core architectures are being increasingly used in embedded systems as they offer several advantages: improved hardware integration, low thermal dissipation and reduced energy consumption, while make it possible to improve the computing power. In order run real-time software on a multicore architecture, Worst-Case Execution Time of every thread should be achievable. This notably involves bounding memory latencies by employing predictable bus arbiter. However, state-of-the-art techniques...
The time predictability of the components a real-time system is required whenever it must be guaranteed that deadlines will met. Research on techniques to evaluate Worst-Case Execution Time (WCET) programs has received much attention these last years but current high-performance processors prove hard model both safely and tightly. We acknowledge difficulty taking into account more dynamic mechanisms within static analysis this motivates our approach consists in making processor fit WCET...
In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software can be implemented in a time analysable way based the proposed hardware primitives. choose to implement primitives memory controller two reasons. Firstly, remove pessimism WCET analysis HRT applications. Secondly, enable that implementation is mostly independent chosen instruction set architecture...
In this paper we present synchronisation techniques for hard real-time (HRT) capable execution of parallelised applications on embedded multi-core processors. We show how commonly used software can be implemented in a time analysable way based the proposed hardware primitives. choose to implement primitives memory controller two reasons. Firstly, remove pessimism WCET analysis HRT applications. Secondly, enable that implementation is mostly independent chosen instruction set architecture...
This study has been carried out in order to determine cost-effective configurations of functional units for multiple-issue out-of-order superscalar processors. The trace-driven simulations were performed on the six integer and fourteen floating-point programs from SPEC 92 suite. We first evaluate number instructions allowed be concurrently processed by execution stages pipeline. then apply some restrictions issue different instruction classes define these configurations. conclude that five...
Multi-core architectures are now considered as possible candidates to implement future time-critical embedded systems. The challenge is make the worst-case execution time (WCET) of each task predictable. In this paper, we investigate bus arbitration schemes with upper-bounded latencies. We focus on heterogeneous workloads in which tasks exhibit distinct requirements terms bandwidth. proposed perform a two-level arbitration: cores organized into groups and all same group benefit from...