A5041695665- Real-Time Systems Scheduling
- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
- Formal Methods in Verification
- Distributed systems and fault tolerance
- Software Testing and Debugging Techniques
- Software System Performance and Reliability
- Software Reliability and Analysis Research
- Advanced Data Storage Technologies
- Software Engineering Research
- AI-based Problem Solving and Planning
- Advanced Software Engineering Methodologies
- Advanced Database Systems and Queries
- Distributed and Parallel Computing Systems
- Robotic Path Planning Algorithms
- Service-Oriented Architecture and Web Services
- Peer-to-Peer Network Technologies
- Model-Driven Software Engineering Techniques
- Control Systems and Identification
- Interconnection Networks and Systems
Institut de Recherche en Informatique de Toulouse
1992-2022
Université Toulouse III - Paul Sabatier
1992-2022
Université Toulouse-I-Capitole
2010-2022
Institut Polytechnique de Bordeaux
2010-2022
Université Toulouse - Jean Jaurès
2010-2022
Centre National de la Recherche Scientifique
2020-2022
Université de Toulouse
2008-2017
Travaux et Recherches Archéologiques sur les Cultures, les Espaces et les Sociétés
2016
This paper presents PapaBench, a free real-time benchmark and compares it with the existing suites. It is designed to be valuable for experimental works in WCET computation may also useful scheduling analysis. bench based on Paparazzi project that represents application, developed embedded different Unmanned Aerial Vehicles (UAV). In this paper, we explain transformation process of applied obtain PapaBench. We provide high level AADL model, which reflects behaviors each component system...
One of the important steps in processing worst case execution time (WCET) a program is to determine loops upper bounds. Such bounds are crucial when verifying real-time systems. In this paper, we propose static loop bound analysis which associates flow and abstract interpretation. It considers binary operators (+, -, *, \) for increment, nested loops, non-recursive function calls, simple conditions (==, !=,, ≫=, &&) values (instead intervals). We present result our on Mälardalen benchmark...
Multi-core architectures are being increasingly used in embedded systems as they offer several advantages: improved hardware integration, low thermal dissipation and reduced energy consumption, while make it possible to improve the computing power. In order run real-time software on a multicore architecture, Worst-Case Execution Time of every thread should be achievable. This notably involves bounding memory latencies by employing predictable bus arbiter. However, state-of-the-art techniques...
For delivering a precise Worst Case Execution Time (WCET), the WCET static analysers need executable program and target architecture. However, prediction (even coarse) of future would be helpful at design stages where only source code is available. We investigate possibility creating predictors based on C using machine-learning (work in progress). If successful, our proposal offer to designer precious information piece early development process.
Following the successful WCET Tool Challenge in 2006, second event this series was organized 2008, again with support from ARTIST2 Network of Excellence. The 2008 (WCC'08) provides benchmark programs and poses a number analysis problems about dynamic, run-time properties these programs. participants are challenged to solve their program tools. Two kinds defined: problems, which ask for bounds on execution time chosen parts (subprograms) benchmarks, under given constraints input data;...
In order to ensure safety of critical real-time systems it is crucial verify their temporal properties. Such a property the Worst-Case Execution Time (WCET), which obtained by architecture-dependent timing analysis and architecture-independent flow fact analysis. this article we present WCET annotation language able express such information originating from user or The open format, named FFX stand for Flow Facts in XML, portable, expandable easy write, understand process.
Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time (wcet) analysis methods tend scale poorly modern hardware architectures. As a result, tradeoff must be made between duration precision analysis, leading an overesti- mation wcet bounds. This in turn reduces schedulability resource usage system. In this paper we present new data structure speed up analysis: eXecution Decision Diagram (xdd), which is ad-hoc extension...
Critical embedded systems are generally composed of repetitive tasks that must meet hard timing constraints, such as termination deadlines. Providing an upper bound the worst-case execution time (WCET) at design is necessary to guarantee correctness system. In static WCET analysis, a main source over-approximation comes from complexity modern hardware platforms: their behavior tends become more unpredictable because features like caches, pipeline, branch prediction, etc. Another software...
Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-case Execution Time (WCET) analysis methods tend scale poorly modern hardware architectures. As a result, trade-off must be found between duration precision analysis, leading an overestimation WCET bounds. In turn, this reduces schedulability resource usage system. article, we present new data structure speed up analysis: eXecution Decision Diagram (XDD), which is ad hoc extension...
The presence of infeasible paths in a program is source imprecision the Worst-Case Execution Time (WCET) analysis. Detecting, expressing and exploiting such can improve WCET estimation or, at least, confidence we have precision. In this article, propose an extension FFX format to express conflicts over detail two ways enhancing analyses with that information. We demonstrate compare these techniques on Malardalen benchmark suite C code generated from Esterel.
Validation of embedded hard real-time systems requires the computation Worst Case Execution Time (WCET). Although these make more and use Components Off The Shelf (COTS), current WCET methods are usually applied to whole programs: analysis require access system code, that is incompatible with COTS. In this paper, after discussing specific cases loop bounds estimation instruction cache analysis, we show in a generic way how static involved can be pre-computed on COTS order obtain component...
The research of a safe Worst-Case Execution Time (WCET) estimation is necessary to build reliable hard, critical real-time systems. Infeasible paths are major cause overestimation theWorst-Case (WCET): without data flow constraints, static analysis by implicit path enumeration will take into account semantically impossible, potentially expensive execution paths, making Path unreachable in practice. We present this paper an approach that allows significantly tighten the WCET identifying...
Temporal property verification is utterly important to ensure safety of critical real-time systems. A main component this the computation Worst Case Execution Time (WCET) that requires, in turn, determination loop bounds. Although a lot efforts have been performed domain, it remains relatively common cases which are unsolved. For example, our knowledge, no fast automatic method can cope with bound simple binary search look-up. In paper, we present an approach solve such loops by using...
This article presents the results of experimenting our OTAWA tool to compute WCETs on a real automotive embedded application. First, we analyze application (C source generated from Simulink models) and exhibit specific properties their implication WCET computation. Then, two very different processor architectures are tested in both cases show (1) how features supported by (2) configure them maximize performances determinism.
In this paper different estimation techniques used for the behavioral partitioning of a hard real-time system over an architecture consisting mixture programmable processors (off-the-shelf processors) and hardware (FPGAs) are presented. The is described at high level abstraction (behavioral description). process breaks up initial description into several parts such that each part can be implemented on software processor while meeting timing constraints or area constraints. Two space...
To automate the transition from specification of a hard real-time system to its design, design aid tool has been defined. It allows description hard-real-time using synchronous visual language, automatic transformation in order comply with temporal constraints indicated specification, and research an optimised configuration for projection on generic architecture.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>