A5034544770- Parallel Computing and Optimization Techniques
- Real-Time Systems Scheduling
- Embedded Systems Design Techniques
- Distributed systems and fault tolerance
- Interconnection Networks and Systems
- Algorithms and Data Compression
- VLSI and Analog Circuit Testing
- Power Systems and Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Network Packet Processing and Optimization
- Smart Grid Energy Management
- Low-power high-performance VLSI design
National University of Singapore
2024-2025
Peking University
2025
Google (United States)
2025
Université Toulouse III - Paul Sabatier
2020-2023
Université Toulouse-I-Capitole
2020-2023
Institut Polytechnique de Bordeaux
2020-2023
Institut de Recherche en Informatique de Toulouse
2020-2023
Université Toulouse - Jean Jaurès
2020-2023
Centre National de la Recherche Scientifique
2020-2023
Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape is diverse, exhibiting trade-offs between performance, efficiency, and architectural specialization. However, CGRAs often overprovision communication resources relative to their modest computing capabilities. This occurs because theoretically provisioned programmability for proves superfluous in practical implementations. In...
Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-Case Execution Time (wcet) analysis methods tend scale poorly modern hardware architectures. As a result, tradeoff must be made between duration precision analysis, leading an overesti- mation wcet bounds. This in turn reduces schedulability resource usage system. In this paper we present new data structure speed up analysis: eXecution Decision Diagram (xdd), which is ad-hoc extension...
Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-case Execution Time (WCET) analysis methods tend scale poorly modern hardware architectures. As a result, trade-off must be found between duration precision analysis, leading an overestimation WCET bounds. In turn, this reduces schedulability resource usage system. article, we present new data structure speed up analysis: eXecution Decision Diagram (XDD), which is ad hoc extension...
We propose a precise and efficient pipeline analysis to tackle the problem of out-of-order resources in modern embedded microprocessors for computation worst-case execution time (WCET). Such are prone timing anomalies (Reineke et al., 2006). To remain sound, must either rely on huge over-estimations or consider all possible states which usually leads combinatorial blowup. cope with this situation, we build an computational model by leveraging algebraic properties decision diagram (Bai 2020)...