Article Free Access Share on A case for two-way skewed-associative caches Author: André Seznec View Profile Authors Info & Claims ISCA '93: Proceedings of the 20th annual international symposium computer architectureJune 1993 Pages 169–178https://doi.org/10.1145/165123.165152Published:01 May 1993Publication History 189citation3,924DownloadsMetricsTotal Citations189Total Downloads3,924Last 12 Months505Last 6 weeks58 Get Citation AlertsNew Alert added!This alert has been successfully added and...

As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardware resources for branch-predictor tables invariably limited, it is not possible to hold all relevant history active branches at the same time, especially large workloads consisting of processes operating-system code. The problem that results, commonly referred as aliasing in tables, many ways similar misses occur...

This paper presents the Alpha EV8 conditional branch predictor The microprocessor project, canceled in June 2001 a late phase of development, envisioned an aggressive 8-wide issue out-of-order superscalar microarchitecture featuring very deep pipeline and simultaneous multithreading. Performance such processor is highly dependent on accuracy its consequently large silicon area was devoted to prediction EV8. relies global history features total 352 Kbits.The focus this different trade-offs...

It has been observed that some applications manipulate large amounts of null data. Moreover these zero data often exhibit high spatial locality. On more than 20% the accesses concern blocks. Representing a block in cache on standard line appears as waste resources.

The TAGE predictor is often considered as state-of-the-art in conditional branch predictors proposed by academy. In this paper, we first present directions to reduce the hardware implementation cost of TAGE. Second show how further misprediction rate through augmenting it with small side predictors.

Phase Change Memory (PCM) may become a viable alternative for the design of main memory systems in next few years. However PCM suffers from limited write endurance. Therefore future adoption as technology will depend on availability practical solutions wear leveling that avoids uneven usage especially presence potentially malicious users. First generation algorithms were designed typical workloads and have significantly reduced lifetime under access patterns try to same line continuously....

In this paper, we present an approach to estimate GPU applications' performance upper bound based on algorithm analysis and assembly code level benchmarking. As example, analyze the potential peak of SGEMM (Single-precision General Matrix Multiply) Fermi (GF110) Kepler (GK104) GPUs. We try answer question how much optimization space is left for why. According our analysis, nature (Kepler) instruction set limited issue throughput schedulers are main limitation factors theoretical performance....

This work demonstrates that a set of commercial and scale-out applications exhibit significant use superpages thus suffer from the fixed small superpage TLB structures some modern core designs. Other processors better cope with at expense using power-hungry slow fully-associative TLBs. We consider alternate designs allow all pages to freely share single, power-efficient fast set-associative TLB. propose prediction-guided multi-grain design uses prediction mechanism avoid multiple lookups in...

The performance of out-of-order processors increases with the instruction window size, In conventional processors, effective cannot be larger than issue buffer. Determining which instructions from buffer can launched to execution units is a time-critical operation complexity size. We propose relieve stage by reordering before they enter This study introduces general principle data flow prescheduling. Then we describe possible implementation. Our preliminary results show that data-flow...

A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents novel cost-effective mechanism called the two-block ahead branch predictor. Information from current instruction block not used for predicting address of next block, but rather following block.This approach overcomes fetch bottle-neck exhibited by wide-dispatch "brainiac" processors enabling them to efficiently predict addresses two blocks...

High performance multi-core processors are becoming an industry reality. Although multi-cores suited for multithreaded and multi-programmed workloads, many applications still mono-thread with a single thread workload is important issue. Furthermore, recent studies suggest that performance, power temperature considerations of future may necessitate activity-migration between cores.Motivated by the above, this paper investigates implications migration on multi-core. Specifically, study...

In this paper, we introduce and analyze the Optimized GEometric History Length (O-GEHL) branch Predictor that efficiently exploits very long global histories in the100-200 bits range. The GEHL predictor features several tables T(i) (e.g. 8) indexed through independent functions of history address. set used lengths forms a geometric series, i.e., L(j) = \alpha ^{i - 1} L(1).This allows to capture correlation on recent outcomes as well old branches. As perceptron predictors, prediction is...

Cache compression seeks the benefits of a larger cache with area and power smaller cache. Ideally, compressed increases effective capacity by tightly compacting blocks, has low tag metadata overheads, allows fast lookups. Previous designs, however, fail to achieve all these goals. In this paper, we propose Skewed Compressed (SCC), new hardware that lowers overheads performance. SCC tracks super blocks reduce overhead, compacts into variable number sub-blocks internal fragmentation, but...

Multi-threaded processors execute multiple threads concurrently in order to increase overall throughput. It is well documented that multi-threading affects per-thread performance but, more importantly, some are affected than others. This especially troublesome for multi-programmed workloads. Fairness metrics measure whether all equally. However defining equal treatment not straightforward. Several fairness multi-threaded have been utilized the literature, although there does seem be a...

Dedicating more silicon area to single thread performance will necessarily be considered as worthwhile in future - potentially heterogeneous multicores. In particular, Value prediction (VP) was proposed the mid 90's enhance of high-end uniprocessors by breaking true data dependencies. this paper, we reconsider concept Prediction contemporary context and show its potential a direction improve current performance. First, building on top research carried out during previous decade confidence...

Poor data layout in memory may generate weak locality and poor performance. Code transformations such as loop blocking or interchanging array padding have addressed this issue for scientific applications. However many generalist applications do not use arrays, but dynamically allocated heterogeneous structures. In paper, we explore two techniques structures: field reorganization, instance interleaving. The application of these be guided by program profiling. This allows significant cache...

Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6, 5]. adds core vector unit capable of 32 double-precision flops per cycle. The fetches data directly from 16 MByte second level cache with peak bandwidth sixty four 64-bit values whole chip backed by memory controller delivering over 64 GBytes/s raw band- width. extends Alpha ISA new instructions that operate on...

Sectored caches have been used for many years in order to reconcile low tag array size and small or medium block size. In a sectored cache, single address is associated with sector consisting on several cache lines, while validity, dirty coherency tags are each of the inner lines.Maintaining major issue designs (e.g. L2 caches). Using design trade-off between which possible large line memory traffic requires size.This technique has including on-chip microprocessor external second level...

This paper presents the Alpha EV8 conditional branch predictor. The microprocessor project, canceled in June 2001 a late phase of development, envisioned an aggressive 8-wide issue out-of-order superscalar microarchitecture featuring very deep pipeline and simultaneous multithreading. Performance such processor is highly dependent on accuracy its predictor consequently large silicon area was devoted to prediction EV8. relies global history features total 352 Kbits. focus this different...

Phase change memory (PCM) technology appears as more scalable than DRAM technology. As PCM exhibits access time slightly longer but in the same range DRAMs, several recent studies have proposed to use PCMs for designing main systems. Unfortunately suffers from a limited write endurance; typically each cell can be only written large still number of times (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> 10...

Sectored caches have been used for many years in order to reconcile low tag array size and small or medium block size. In a sectored cache, single address is associated with sector consisting on several cache lines, while validity, dirty coherency tags are each of the inner lines. Usually line location statically linked one only word location. decoupled introduced paper, this monolithic association broken; dynamically chosen at fetch time among possible locations. The volume same range as...

In this paper, we introduce and analyze the Optimized GEometric History Length (O-GEHL) branch Predictor that efficiently exploits very long global histories in 100-200 bits range. The GEHL predictor features several tables T(i) (e.g. 8) indexed through independent functions of history address. set used lengths forms a geometric series, i.e., L(j) = /spl alpha//sup j-1/L(1). This allows to capture correlation on recent outcomes as well old branches. As perceptron predictors, prediction is...