Threshold voltage fluctuation has been experimentally studied, using a newly developed test structure utilizing an 8 k-NMOSFET array. It shown that both V/sub th/ and the channel dopant number n/sub a/ distributions are given as Gaussian function, verified standard deviation of a/, can be expressed square root average which is consistent with statistics. In this study, it (/spl delta/V/sub th/) mainly caused by statistical explains about 60% experimental results. Moreover, we discuss briefly...

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics been experimentally studied compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique film relaxed-Si/sub 0.9/Ge/sub 0.1/ layer the conventional SIMOX process, (20 nm thickness) fully relaxed-SiGe (340 thickness)-on-buried oxide (100 was formed, n-and p-channel were...

A novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers, i.e., insulator (SGOI), with a high Ge fraction is proposed demonstrated application to strained-Si metal-oxide-semiconductor field effect transistors (MOSFETs). This based the high-temperature oxidation of SGOI lower fraction. It found that atoms are rejected from condensed in layers. The conservation total amount layer confirmed by structural compositional analyses dry-oxidized at 1050°C different...

A compact, high-resolution analog-to-digital converter (ADC) especially for sensors is presented. The basic structure a completely digital circuit including ring-delay-line with delay units (DUs), along frequency counter, latch, and encoder. operating principles are: (1) the time of DU modulated by (A/D) conversion voltage (2) pulse passes through number DUs within sampling (= integration) which output as data. Compact size high resolution were realized an ADC having area 0.45 mm <sup...

This paper reviews the current critical issues regarding device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics challenges strained-SOI CMOS technology are presented, on basis our recent results. Furthermore, a future possible direction channel engineering using strained-Si/SiGe structures, into deep sub-100 nm regime, is addressed.

We have developed high-performance strained-SOI CMOS devices on thin film relaxed SiGe-on-insulator (SGOI) substrates with high Ge content (25%) fabricated by the combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation (ITOX) techniques without using SiGe buffer structures. The maximum enhancement electron hole mobilities against universal mobility amounts to 85 53%, respectively. On other hand, we also observed reduction carrier in a thinner strained-Si layer or...

The Ge depth profile and generation of dislocations associated with oxidation SiGe-on-insulator (SGOI) substrates are examined from the viewpoint temperature dependence. It is found that profiles in SGOI layers after strongly dependent on temperature. This fact explained by competitive process between accumulation atoms at SiGe/thermal oxide interface, determined rate, diffusion toward during substrates. While abrupt obtained low-temperature causes dislocations, high content no can be...

We have newly developed [110]-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying condensation technique to SiGe layers grown SOI wafers. demonstrated that electron hole mobility enhancement strained-SOI devices amounts 23% 50%, respectively, against mobilities unstrained MOSFETs. As a result, ratios MOSFETs universal (100)-surface bulk-MOSFETs increase up 81% 203%, respectively. Therefore,...

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed demonstrated. This device has an ultrathin SiGe channel layer, which is directly sandwiched by gate oxide buried layers. The mobility enhancement 2.3 times higher than the universal conventional Si pMOSFETs was obtained for with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ formed high-temperature oxidation 0.9/Ge/sub 0.1/ layer grown on Si-on-insulator (SOI) substrate. fully depleted SGOI MOSFET...

This paper presents a quantitative study on the device design for control of threshold-voltage and suppression short-channel effects (SCEs) in ultrathin strained-silicon-on-insulator (strained-SOI) CMOSFETs sub-100-nm regime. A two-dimensional simulation is used this purpose, with emphasis impact band offset Si/SiGe heterostructures. For threshold-voltage, combination gate work function back bias needed to obtain appropriate values n- p-channel MOSFETs suppress SiGe buried channels thicker...

We have experimentally studied the high-lateral-field carrier velocity near source edge in sub-0.1 /spl mu/m MOSFETs. It is demonstrated that high-field electron and hole universal low-field mobility dependence. This shows lower than due to hole's mobility. Moreover, we investigated low-power CMOS operation using overshoot. verified there a most suitable supply voltage for improving The shown be about 1 V. Therefore, overshoot will very useful low future.

We have newly developed an advanced SOI p-MOSFET with strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separation-by-implanted-oxygen) technology. The characteristics of this strained-SOI substrate and electrical properties MOSFETs been experimentally studied. Using strained-Si/relaxed-SiGe epitaxy technology usual process, we successfully formed the layered fully-strained-Si (20 nm)/fully-relaxed-SiGe film (290 nm) uniform buried oxide layer (85 inside SiGe...

A 16-Mbit DRAM fabricated with a 0.6- mu m triple-well CMOS technology on an n-substrate is described. The fast RAS access time of 45 ns has been achieved by the use structure, optimized chip architecture, and decoded word-line bootstrap driver. An advanced trench capacitor cell area 4.8 m/sup 2/ realized introducing quarter-pitched memory array arrangement. three-way voltage-down conversion system enhances RAM performance as well reliability. measures 7.87*17.4 mm/sup 2/.< <ETX...

We have experimentally and analytically studied the influence of statistical spatial-nonuniformity dopant atoms on threshold voltage V th in a system many metal-oxide-semiconductor field-effect-transistors (MOSFETs). According to experimental results our analytical model, it is found that nonuniformity along channel (the lateral nonuniformity) causes unstable drain bias d dependence , whereas standard deviation has weak . Moreover, substrate fluctuates due vertical which perpendicular...

We have developed a technology for relaxing top SiGe layers with low dislocation density on Si substrates, without using thick buffer structures. By introducing thin strained layer and the internal-oxidation (ITOX) process following separation-by-implanted-oxygen (SIMOX) process, we experimentally demonstrated relaxed SiGe-on-insulator (SGOI) substrates Ge content of 20%, it has been realized that their is factor 20 lower than SGOI layer.

In this paper, fabrication of the dual channel CMOS devices based on Ge-condensation technique is demonstrated as well their mobility and current drive enhancements. Ge-rich strained SGOI pMOSFETs were integrated with Si/SGOI nMOSFETs by a process combined Ge condensation process, in which strain layers properly controlled. As result, significant electron- hole-mobility enhancements for SOI channels observed Id

We have proposed a new MOSFET structure, strained-Si/Si/sub 0.9/Ge/sub 0.1/-on-Insulator (SSGOI) MOSFETs applicable to the sub-100 nm generation. This SSGOI structure was successfully fabricated by combination of SIMOX technology and Si re-growth technique. The strained-Si in found good crystal quality very flat interfaces. p-MOSFETs exhibited FET characteristics. It demonstrated, for first time, that hole mobility is higher universal conventional p-MOSFETs.

We have recently developed [110]-surface strained silicon-on-insulator (SOI) n-MOSFETs. The strained-silicon (Si) layer with the strain of about 0.6% has been fabricated on a relaxed SiGe-on-insulator (SGOI) structure germanium (Ge) content 25%. electron mobility characteristics along various current directions experimentally studied and compared to those [100]- unstrained-bulk MOSFETs. demonstrated, for first time, that [110] strained-SOI MOSFETs is enhanced, enhancement depends...

The authors have fabricated 0.10- mu m gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were using an LDD structure combined a self-aligned TiSi/sub 2/ process. Channel doping optimized so as suppress punchthrough well realize transconductance low drain junction capacitance. exhibited well-suppressed band-to-band tunneling current, although the...

We have developed the source-heterojunction-MOS-transistor (SHOT), a novel high-speed MOSFET with relaxed-SiGe/strained-Si heterojunction source structures for quasi-ballistic or full-ballistic transistors. Using band-offset energy at SiGe/strained-Si heterojunction, high velocity electrons can be injected into strained-Si channel from SiGe region. For first time, we experimentally demonstrated that transconductance is enhanced in SHOT applied drain voltage, compared to of strained- and...

In this paper, we have studied [110]-surface strained-SOI n- and p-MOSFETs with higher carrier mobility, according to the reduced interband/intervalley scattering smaller effective mass of carriers even in [110] strained-Si channel. The channel has been formed on relaxed-SGOI substrates, fabricated by Ge condensation technique (25%) a SOI substrate. It is demonstrated, for first time, that electron hole mobility enhancements devices amount 23% 50%, respectively, against those...