A5034189661- Analog and Mixed-Signal Circuit Design
- CCD and CMOS Imaging Sensors
- Advancements in PLL and VCO Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Fiber Optic Sensors
- Radio Frequency Integrated Circuit Design
- Photonic Crystal and Fiber Optics
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Digital Filter Design and Implementation
- Optical Network Technologies
- Sensor Technology and Measurement Systems
- Advanced Adaptive Filtering Techniques
- Analytical Chemistry and Sensors
- Numerical Methods and Algorithms
- Conservation, Biodiversity, and Resource Management
- PAPR reduction in OFDM
- Land Use and Ecosystem Services
- Low-power high-performance VLSI design
- Glass properties and applications
- Advanced Wireless Communication Techniques
- Advanced Fiber Laser Technologies
- Optical Systems and Laser Technology
- Plasmonic and Surface Plasmon Research
- Microfinance and Financial Inclusion
Institute of Microelectronics
2016-2025
Chinese Academy of Sciences
2016-2025
Yanshan University
2008-2024
Institute of Geographic Sciences and Natural Resources Research
2022-2024
Institute of Semiconductors
2024
Jiangxi Agricultural University
2023-2024
University of Chinese Academy of Sciences
2017-2023
Shandong University of Finance and Economics
2022
Peking University
2017-2018
Hospital of Hebei Province
2017
Circuit probe (CP) test data for a wafer encapsulates the comprehensive electrical characteristics of each integrated circuit (IC) chip, making accurate analysis this set crucial quality control within semiconductor industry. This paper introduces novel methodology analyzing IC dies based on their CP set. Initially, three-dimensional matrix, termed wafer_Q_set, is constructed by extracting information from Subsequently, wafer_Q_set reduced to two dimensions utilizing fractal theory and...
ABSTRACT This paper presents a proposed inverter‐based triple‐tail comparator designed for high‐speed and high‐efficiency applications in analogue‐to‐digital converters. In this comparator, auxiliary inverter based pre‐amplifier is to maintain the gain of pre‐amplification stage bolstering robustness pre‐amplifier. Combined with offset cancelled technique, definite state each prior comparison eliminates hysteresis effects. Utilizing 28 nm CMOS process, achieves data conversion rate 2 GHz...
In the context of implementation rural revitalization strategy, industrialization agriculture and areas is rapidly increasing, more capable people in management are actively leasing land to develop modern agriculture, broaden diversified livelihood channels, pursue sustainable development. We used leased-in farmland households as an entry point, focusing on development industries choice strategies fill a gap existing literature. Based theory, we constructed analysis framework for using...
By the study of a series molecular liquids fragilities covering almost entire known range by mechanical spectroscopy quantitatively monitoring healing stress-induced microcracks recently developed W. H. Wu et al. [Appl. Phys. Lett. 92, 011918 (2008)], we show that cracking temperature coincides with onset glass Tg, quite independent liquid fragility. Another interesting observation is major part modulus recovery occurs below Tg. Thus, our establishes an additional approach to dynamics and...
This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock suppress time skew between channels. Based on segmented pre-quantization and bypass switching scheme, double alternate comparators...
This article proposed a deep-pipelined analog-to-digital converter (ADC) that utilizes an input-split fully differential ring amplifier (ringamp, RAMP). The implemented ringamp is optimized for speed, achieving higher nondominant pole frequency, and exhibits excellent adaptability in low-voltage, deep-nanoscale advanced CMOS processes. To minimize nonoverlap time, nonoverlapping clock generator employed, generating two-phase clocks with near 50% duty cycles sampling amplification the...
This paper presents a 12-bit 1.6 GS/s pipelined analog-to-digital converter (ADC) in 40-nm CMOS process. A novel dual-capacitor dither injection technique was proposed, based on randomize multi-level uniform logic, aimed at leveraging signal jitter to disperse higher-order harmonics and spurious signals within the spectrum. The proves highly effective preserving linearity of high-speed pipeline ADCs under Process, Voltage, Temperature (PVT) variations. Additionally, amplifier with SC net...
This article presents a high-output-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter, in which 4-tap hybrid feed-forward equalizer (FFE) employing both fractionally-spaced pre-emphasis (FS-PE) and baud-spaced de-emphasis (BS-DE) is proposed. The PE technique enlarges the output swing by directly stacking pre-distortion pulses, naturally consumes less power as it boosts only desired symbols. FS-based pre/post1 taps equalize high-frequency loss, provide wide compensation...
This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes high-linearity input buffer and two-step input-split fully differential ring amplifier (ringamp). The implemented based on gain-boost cascode current source, is optimized for linearity over wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode power-supply rejection, employed as the residue amplifier. Additionally, correlation-based...
This brief presents an 8 GSps 14 bit current steering RF digital-to-analog converter (DAC) for communication system. Double edge sampling method is adopted to reduce maximum clock frequency. To suppress the third-order intermodulation (IM3), switch driver with enhanced reset circuit proposed. An improved dynamic element matching (DEM) based on optimized switching sequence adopted. According experimental result, measured IM3 below -62 dBc up 3.6 GHz. The digital interpolation and...
Soil erosion results in land degradation and desertification northern China. The Xilingol League of Inner Mongolia is an important part the “Two Barriers Three Belts”, has been given main function “a windbreak sand-fixing belt China”. Accurate measuring soil moduli, analyzing differences moduli across different periods regions, are basis for carrying out conservation evaluating effectiveness ecological governance. Some radioisotopes good environmental tracers because they closely combined...
This paper examines the distinct effects of actual and perceived security on forestland investment by rural households. To achieve this, we utilized Tobit IV-Reg models to analyze repeated survey data from 500 households residing in 50 villages Jiangxi Province during years 2017 2018. We measured households’ forest management labor cash inputs. The findings indicate that tenure significantly influence investment. Specifically, possession certificates exhibiting a marked increase However,...
This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due channel mismatches. An early comparison scheme used minimize non-overlapping time, where custom-designed latch developed replace typical generator. By using dither capacitor generate an equivalent direct current input, zero-input-based calibration correct mismatch inter-stage gain...