This paper presents a SerDes receiver for medium-reach interconnection in 28-nm CMOS process. It employs CTLE and an adaptive quarter-rate loop-unrolling 5-tap DFE utilizing SS-LMS algorithm to enable adjustment of tap coefficients under different channels. The proposed contains CML-based summer with CMFB technology two-stage dynamic comparator offset calibration loop. Simulation results show that this can operate at 25 Gb/s data rate power efficiency 5.99 pJ/bit, Its BER is less than 1E-12...

This article presents a high-output-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter, in which 4-tap hybrid feed-forward equalizer (FFE) employing both fractionally-spaced pre-emphasis (FS-PE) and baud-spaced de-emphasis (BS-DE) is proposed. The PE technique enlarges the output swing by directly stacking pre-distortion pulses, naturally consumes less power as it boosts only desired symbols. FS-based pre/post1 taps equalize high-frequency loss, provide wide compensation...

In this letter, we present a novel analysis and design approach of self-oscillation frequency (SOF) for 0.8-μm indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) emitter-coupled logic (ECL) current-mode (CML) static dividers. SOF ECL CML dividers is designed to be the maximum value after theoretical multiparameter optimization. The results show that divider 62 37.5 GHz, respectively. With sinusoidal waveform input, operating range from 0.1 65 55 while cut-off f <sub...

This letter presents a broadband 2:1 static ECL frequency divider in 0.8 μm InP DHBT process. The proposed is based on an double emitter-followers structure. maximum cut-off (ft) utilization of the device improved up to 0.967 through theoretical analysis and calculation. measurement shows that can operate with input from 1 GHz 62 sinusoidal waveform, while ft 150 GHz. Bandwidth BW/ft 0.413, which extremely high value for devices at same size.

In this letter, we present a 25-GSa/s wideband track-and-hold amplifier using 0.8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> indium phosphide (InP) process for high-speed analog sampling front-end. design, an active peaking input buffer is first used in the base–collector switching diode sampler. Moreover, it carefully calculated and analyzed. The dominant...

In this brief, a high-speed wideband track-and-hold amplifier (THA) is implemented in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.8~{\mu }\text{m}$ </tex-math></inline-formula> InP double-heterojunction bipolar transistor (DHBT) process. This THA based on base-collector (b-c) switching diode architecture and achieves −3 dB bandwidth of 35 GHz at sampling rate 30 GSa/s. For the first time, an enhanced...

A broadband static frequency divider fabricated in a 165GHz ft 0.8μm InP DHBT process is described. Capacitive degeneration technique adopted, extending the operating bandwidth with little increase power consumption and area occupancy. The device characteristics are analyzed to achieve high utilization. chip occupies 0.484mm×0.44mm consumes 380mW from dual supplies of -2.5V -3.5V. measured input-referred self-oscillation (SOF) 56GHz, output locates -5.87∼1.87dBm. With single-ended sine-wave...

This letter presents a wideband high-speed static 1/2 frequency divider using 0.8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> indium phosphide (InP) process. In this design, some performance-enhanced unity-gain ( notation="LaTeX">${f_{T}}$ ) doubler structures are proposed and compared. Moreover, the application of an enhanced -doubler technique, for first...

This paper presents a 2: 1 analog multiplexer (AMUX) using IHP's 130-nm SiGe BiCMOS process. The proposed AMUX expands the bandwidth (BW) of CMOS-based DACs by introducing interleaving sampling technique, thus improving data rate single lane in modern optical communication systems. Meanwhile, detailed analysis process selection which particularly focuses on material and device considerations is adopted, principle BW expansion comprehensively discussed. exhibits >70 GHz, achieving 200 Gb/s...

This letter presents a wideband and high conversion gain mixer based on Gilbert-cell in InP DHBT process. Capacitive degeneration is introduced to increase the bandwidth of with no voltage drop few cost area. Current bleeding technique employed improve gain. Utilization device ft analyzed achieve 0.919. The measurement demonstrates 14.5 dB at 26 GHz -3 49 GHz. BW/ft 0.306 GBP 260 are obtained, which believed be among best compared mixers fabricated same size

A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated a 0.8-μm indium phosphide (InP) process with 165 GHz cut-off frequency ( fT). Broadband operation achieved using an enhanced degenerated Darlington fT-doubler buffer, which first used the switched-emitter follower (SEF) architecture. Compared traditional structures, cascode structure reduces "VCE mismatch" between amplifying transistors. Moreover, it can also achieve higher...

This work presents a transformer matching X band MMIC power amplifier (PA) on gallium nitride (GaN) process. A port impedance modeling-based design method is proposed and analyzed. The simplifies the network process, improves accuracy, relieves designer's burden. novel compact temperature compensation (TC) circuit also used in this design. PA 0.25µm GaN technology occupies 1.594mm2 area. At 28V supply, gain output of reaches 15dB 29dBm respectively. Additionally, designed TC stabilizes...