To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for serial links. Interleaved SAR achieve high sampling speeds and good energy efficiency. However a challenge is that these are large therefore suffer from interleaving artifacts related to size [1]. Compact, efficient needed address this problem. As an alternative, multiple-bit-per-cycle deliver speed single ADC, but at the cost of significant added complexity (i.e., extra quantizers capacitor DACs)...

As IoT is increasingly integrated into our everyday life, the demand for different sensor modalities, especially imaging, rising. imagers are often compact and have small form-factor batteries thus must be designed with both low power (improving battery life) high image quality (maximizing utility). Previously reported sensors [1, 2], along this work, adopt motion-detection (MD) triggering of full-array capture where MD performed on a heavily subsampled frame to enable continuous low-power...

We propose a low-power image sensor with motion-based triggering feature for the Internet of Things (IoT) applications. The supports near-pixel [within analog-to-digital converter (ADC)] motion-detection mode run on heavily subsampled frame (32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 20 pixels, while consuming only 1.7 notation="LaTeX">$\mu \text{J}$ /frame) to...

The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) are solution a high-resolution ADC having tolerance analog component errors. reduces input temporal noise well quantization error itself [1]. However, an I-ΔΣ also classified slow because it requires exponential time get higher bit resolution. To...

Piezoelectric energy harvesters (PEHs) are widely deployed in many self-sustaining systems, and proper rectifier circuits can significantly improve the conversion efficiency and, thus, increase harvested energy. Various active rectifiers have been proposed past decade, such as synchronized switch harvesting on inductor (SSHI) synchronous electric charge extraction (SECE). This article presents a sense-andset (SaS) that achieves maximum-power-point-tracking (MPPT) of PEHs maintains optimal...

Programmability is one of the most significant advantages a digital phase-locked loop (PLL) compared with charge-pump PLL. In this paper, PLL that extends programmability to include noise introduced. A digitally controlled oscillator (DCO) using switched capacitor for frequency feedback proposed maintain constant figure merit while reconfiguring its performance. The DCO offers an accurate and linear tuning curve insensitive environmental changes. detection circuit statistical property...

This article presents a low jitter, power, reference spur LC oscillator-based oversampling digital phase locked loop (OSPLL). The proposed architecture simultaneously offers in-band noise, wide-bandwidth, and spur. In addition, this proposes an digitally controlled oscillator (DCO) for the OSPLL to achieve fast frequency update fine resolution, while its varactor switching timing is set optimally jitter using DCO tuning pulse control scheme. was fabricated in 28-nm CMOS process. integrated...

Digital PLLs are popular for on-chip clock generation due to their small size and technology portability. Variability tolerance is a key design challenge when designing such in an advanced CMOS technology. Environmental variations, as mismatch, process, supply voltage, temperature (PVT) perturb device characteristics result performance changes, DCO gain noise. Another consideration the wide range of operating modes which modern digital circuits (e.g., processors) operate. For instance,...

Piezoelectric energy harvesters (PEHs) convert mechanical from vibrations into electrical energy. They have become popular in energy-autonomous IoT systems. However, the total extracted by a PEH is highly sensitive to matching between impedance and extraction circuit. Prior solutions include use of full-bridge rectifier (FBR) so-called synchronous electric-charge (SECE) [1], are suitable for non-periodic vibrations. their efficiency low since large internal capacitance C <sub...

IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs typically used for readout as energy efficient easy to multiplex across many sensors. However, achieving (>14b) is challenging all factors limiting performance (resolution, mismatch, noise) must be simultaneously addressed with minimal impact. In this paper, we present an energy-efficient, capacitor-array-assisted cascaded charge-injection ADC...

We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal spatial sparsity in sequence. This approach reduces energy consumption spent processing transmitting unimportant data achieve a 16 × imaging system gain intruder detection scenario. The ISP was fabricated 40-nm CMOS consumes only 170 μW at 5 frames/s for neural network-based 192 compressed recording.

This work presents an acoustic analog front-end based on a delta sigma-modulated sample and average common-mode feedback technique. The proposed offers process temperature stable high pass (HP) frequency corner, unity dc gain, programmable HP corner to reduce startup time. In addition, this article also automatic saturation detection recovery technique from in-band input artifacts. was implemented in the low-noise amplifier (LNA) gain (PGA) of fabricated 180-nm CMOS. achieved maximum...

This paper presents a switched-bias MEMS microphone preamplifier for an ultra-low-power voice interface. A switched-MOSFET periodically changes the MOSFET between strong inversion and accumulation to inherently reduce 1/f noise. In addition, proposed coupling capacitor allows benefit from high bias voltage while preamp can use low VDD. The achieves 7.3μVrms input referred noise (A-weighted) with 3.4μA, improving NEF by 4.5×. Acoustic testing shows 61.3dBA SNR at 94dB SPL.

In this work, we propose an X0 design with frequency -divided (4kHz), high energy-to-noise-ratio pulse-injection oscillation (HERO). The performance of the is compared state-of-the-art X0s in Fig. 3.3.6. By allowing crystal to run freely for a longer time between injections, HERO achieves 2ppb Allan deviation floor, which 5x lower than floors among state-ofthe-art nW X0s. Furthermore, less-frequent injections significantly reduce injection overhead, enabling lowest-reported power consumption...

This letter proposes an instrumentation amplifier for neural recording applications whose measured noise efficiency factor (NEF) is 2.2. A discrete-time parametric adopted as a preamplification stage to lower the input-referred noise, thus improving NEF. The additional induced sampling minimized by oversampling, and power overhead switching adopting 8-phase soft-charging technique.

A 0.88 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD optimized in pipelined look-ahead architecture to reach 10 Gb/s at 5.8 pJ/b and 5 3.9 pJ/b, making it practical an energy-efficient ADC-based link. Compared linear equalizer decision feedback equalizer, the provides...

We present a triaxial MEMS accelerometer readout circuit (RoC) with 40× signal gain using high bias voltage, reducing power by eliminating the need for chopped AFE chain. The proposed RoC achieves 121µg/√Hz input referred noise and 1.5g dynamic range at 184nW per-axis power, while maintaining <1% non-linearity mechanical full-scale of >20 g, improving FoM 15.6×.

Recent advances in circuits have enabled significant reduction the size of wireless systems such as implantable biomedical devices. As a consequence, battery integrated these has also shrunk, resulting high internal resistances (~10kΩ). However, peak-current requirement power-hungry components radios remains mW range, and hence cannot be directly supplied from battery. Therefore, duty-cycled architectures pulsed-based been proposed that transmit short burst (~1μs) power (~10mW) by an energy...

An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing scheme for optimal phase noise. Designed 28-nm CMOS process, the achieves 67.1-fs RMS-jitter 5.2-mW power consumption, which translates to -256-dB FoM. The in-band noise of -130 dBc/Hz at 4-GHz output frequency. spur -78 dBc.

Devices based on the spin as fundamental computing unit provide a promising beyond-complementary metal-oxide-semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. One such option is Magneto-Electric Spin-Orbit (MESO) device, an attojoule-class emerging technology extend Moore's law. This paper presents circuit design optimization techniques stacking canary circuit-based asynchronous clock pulse generation scheme for technology. With these targeted...

This paper proposes a 2.2 noise efficiency factor (NEF) instrumentation amplifier for neural recording applications. A parametric based on the MOS C-V characteristic is designed as pre-amplifier stage, lowering input referred of following stages by 3.4×. Sampling minimized oversampling signal and switching power reduced adopting an 8-phase soft-charging technique.

This article introduces a 32-kHz crystal oscillator (XO) with high energy-to-noise-ratio pulse injection at subharmonic frequency. A T/4-delay clock slicer is proposed to convert the sinusoidal waveform into an output of 32 kHz and introduce delay T/4, providing proper timing for energy injections. The feeds frequency dividers generates pulses activate all-NMOS differential driver 4 kHz. It enables two injections in eight periods peak valley oscillation, running freely between configuration...

Millimeter-scale embedded sensing systems have unique advantages over larger devices as they are able to capture, analyze, store, and transmit data at the source while being unobtrusive covert. However, area-constrained pose several challenges, including a tight energy budget peak power, limited storage, costly wireless communication, physical integration miniature scale. This paper proposes novel 6.7$\times$7$\times$5mm imaging system with deep-learning image processing capabilities for...

We propose an ultra-low power (ULP) Image Signal Processor (ISP) that performs on-the-fly in-processing frame (de)compression and hierarchical event recognition to exploit the temporal spatial sparsity in image sequence achieve a 16× imaging system energy gain. The ISP is fabricated 40 nm CMOS consumes only 170 μW at 5 fps for neural network-based intruder detection 192× compressed recording.

This letter describes an analog-assisted digital LDO that cascades a conventional structure with single, large output pMOS biased in subthreshold to enable fast response voltage droop. By digitally controlling the gate of pMOS, operating regime transistor is decoupled from input voltage. In addition, 2-pF capacitor between and creates high-pass path boost current when droops occur. The proposed design fabricated 28-nm CMOS, it enables uniform transient over range 0.5-0.9 V. measured droop...