Rohit Rothe

ORCID: 0000-0003-0300-1909
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Research Areas
  • Ferroelectric and Negative Capacitance Devices
  • Analog and Mixed-Signal Circuit Design
  • Acoustic Wave Resonator Technologies
  • Advanced MEMS and NEMS Technologies
  • Radio Frequency Integrated Circuit Design
  • Blind Source Separation Techniques
  • Mechanical and Optical Resonators
  • Advanced Power Amplifier Design
  • Indoor and Outdoor Localization Technologies
  • Multilevel Inverters and Converters
  • Network Packet Processing and Optimization
  • Advanced Adaptive Filtering Techniques
  • Microwave Engineering and Waveguides
  • Sensor Technology and Measurement Systems
  • Magnetic properties of thin films
  • Music and Audio Processing
  • Text and Document Classification Technologies
  • Ultra-Wideband Communications Technology
  • Advanced DC-DC Converters
  • Geophysics and Sensor Technology
  • Advanced Memory and Neural Computing
  • Photonic and Optical Devices
  • Induction Heating and Inverter Technology
  • Advanced Electrical Measurement Techniques
  • Microwave Imaging and Scattering Analysis

University of Michigan
2019-2024

Indian Institute of Technology Bombay
2019

This article presents a voice and acoustic activity detector that uses mixer-based architecture ultra-low-power neural network (NN)-based classifier. By sequentially scanning 4 kHz of frequency bands down-converting to below 500 Hz, feature extraction power consumption is reduced by 4×. The NN processor employs computational sprinting, enabling 12× reduction. system also features inaudible signature detection for intentional remote silent wakeup the while re-using subset same components....

10.1109/jssc.2019.2936756 article EN IEEE Journal of Solid-State Circuits 2019-09-12

This work presents an acoustic analog front-end based on a delta sigma-modulated sample and average common-mode feedback technique. The proposed offers process temperature stable high pass (HP) frequency corner, unity dc gain, programmable HP corner to reduce startup time. In addition, this article also automatic saturation detection recovery technique from in-band input artifacts. was implemented in the low-noise amplifier (LNA) gain (PGA) of fabricated 180-nm CMOS. achieved maximum...

10.1109/jssc.2021.3135899 article EN IEEE Journal of Solid-State Circuits 2022-01-10

We propose a fully integrated low-power keyword spotting (KWS) system on chip (SoC) with content-adaptive frame subsampling, implemented in 28-nm CMOS technology. The is co-optimized from end-to-end including the analog frontend (AFE) and digital backend skip-recurrent neural network (RNN) KWS algorithm. SoC performs dynamic power gating based decision skip-RNN algorithm that allows opportunistic skipping to reduce consumption without compromising accuracy. design employs fast-stabilizing...

10.1109/jssc.2023.3316648 article EN IEEE Journal of Solid-State Circuits 2023-10-03

We present a triaxial MEMS accelerometer readout circuit (RoC) with 40× signal gain using high bias voltage, reducing power by eliminating the need for chopped AFE chain. The proposed RoC achieves 121µg/√Hz input referred noise and 1.5g dynamic range at 184nW per-axis power, while maintaining <1% non-linearity mechanical full-scale of >20 g, improving FoM 15.6×.

10.1109/vlsitechnologyandcir46769.2022.9830230 article EN 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2022-06-12

Devices based on the spin as fundamental computing unit provide a promising beyond-complementary metal-oxide-semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. One such option is Magneto-Electric Spin-Orbit (MESO) device, an attojoule-class emerging technology extend Moore's law. This paper presents circuit design optimization techniques stacking canary circuit-based asynchronous clock pulse generation scheme for technology. With these targeted...

10.1109/jxcdc.2023.3322292 article EN cc-by-nc-nd IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 2023-10-05

Keyword spotting (KWS) has become essential as a wake-up mechanism for edge loT devices. While recent advances in deep learning have improved KWS accuracy [1], reducing system power consumption remains challenge. A typical signal chain consists of an analog frontend (AFE), feature extractor (FE), and neural network classifier (NN). To reduce total power, all three blocks must be carefully co-optimized. Recent work reported 0.51 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML"...

10.1109/isscc42615.2023.10067808 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2023-02-19

We present a Sample and Average Feedback Resistor (SAFR) for accurate programmable common-mode feedback in capacitively coupled low-power amplifiers. Using only switches, clocks, capacitors, we reduce the variation across process temperature by 4.4× 226x, respectively, compared to traditional pseudo-resistor implementation. The SAFR was implemented audio LNA + PGA ADC chain, achieving resistance of 100 TΩ HP corner programmability from 16 mHz 4 Hz.

10.1109/vlsicircuits18222.2020.9162804 article EN 2020-06-01

This article presents a triaxial microelectromechanical system (MEMS) capacitive accelerometer using high-voltage biasing technique to achieve high resolution with ultralow power. The generates differential pair of voltages bias the MEMS structure, raising signal substantially above noise floor analog front-end (AFE) circuits. With consequent increased signal-to-noise ratio (SNR), proposed eliminates need for power-hungry low-noise amplifier (LNA) and chopping which significantly improves...

10.1109/jssc.2024.3349861 article EN IEEE Journal of Solid-State Circuits 2024-01-15

10.1109/vlsitechnologyandcir46783.2024.10631439 article EN 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 2024-06-16

We present an acoustic analog front-end with a 100TΩ feedback resistance that is robust to PT variation (1.8× deviation across –40 80°C and 0.035× σ/µ 16 measured samples) achieves 3.3× reduction in input referred noise (IRN). It eliminates frequency phase dependent systematic offset introduced by similar previous technique [5] introduces automatic saturation detection modulation for fast amplifier restabilization, yielding 10× improvement artifact recovery time. The was implemented 192 nW...

10.23919/vlsicircuits52068.2021.9492374 article EN Symposium on VLSI Circuits 2021-06-13

This paper presents an improved Second Order Input Intercept Point (IIP2) Direct Conversion Mixer architecture by introducing chopping in the standard active double balanced mixer. The mixing frequency required is half of RF frequency. technique improves second order linearity There only one mixer signal path enabling low power design. Simulation results for enhanced are compared with a An IIP2 improvement around 8 dB demonstrated.

10.1109/vlsid.2019.00042 article EN 2019-01-01

Emerging loT applications, such as asset tracking and first-responder rescue operation, require a new localization solution that achieves decimeter-level accuracy for long range (km) in GPS-denied indoor non-line-of-sight (NLOS) scenarios. Impulse-response ultra-wideband radar (IR-UWB) [1]–[3] can achieve high precision, but cannot operate distance NLOS conditions due to FCC-regulated transmit-power limits severe pathloss through walls. Moreover, IR-UWB requires very instantaneous power (>...

10.1109/isscc42614.2022.9731780 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2022-02-20
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