A5035467279- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- CCD and CMOS Imaging Sensors
- Sensor Technology and Measurement Systems
- Magnetic Field Sensors Techniques
- Analytical Chemistry and Sensors
- Low-power high-performance VLSI design
- Asian Culture and Media Studies
- Electrical and Bioimpedance Tomography
- Neural Networks and Applications
- Neuroscience and Neural Engineering
- Advanced Battery Technologies Research
Sogang University
2020-2025
This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For single-temperature trimming, β-compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this proposes dynamic element matching (DEM) low-pass filtering which employs the decimation filter of delta-sigma analog-to-digital converter (ADC) in digital domain....
This paper presents a CMOS analog front-end (AFE) for hall sensor readout IC. A three- operational amplifier-based instrumentation amplifier (IA) is employed low noise amplification with high common mode rejection ratio. To address the input offset of magnetic sensor, an internal cancellation circuit using R-2R DAC adopted. 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order incremental ADC used to convert amplified into 16-bit...
This paper presents a single-trim switched-capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. A β-compensation technique, which is used in conjunction with mismatch averaging, and discrete time (DT) domain curvature correction are proposed to minimize non-PTAT errors. The remaining PTAT errors cancelled out by using single room-temperature (27°C) trimming. Implemented 0.18μm CMOS, the SC BGR achieves 3σ inaccuracy of +0.02%, -0.12% an average temperature...
This work proposes two versions of a 12 b 100 MS/s successive-approximation register (SAR) ADC based on non-binary C-R hybrid DAC. The proposed DAC applies weighted capacitor array to the 7 MSBs meet settling requirement output and determines remaining 5 LSBs using reference voltages generated from simple resistor string reduce area significantly. Version 1 in 28 ㎚ CMOS adopts synchronous SAR logic comparator with tail reset switch minimize power consumption. 2 0.18 ㎛ employs an asynchronous...
This paper presents a 2SUPnd/SUP order modified feed-forward (FF) delta-sigma modulator. To reduce power consumption, the proposed analog-to-digital converter (ADC) adopts class-AB op-amp for first integrator since it shows an enhanced slew rate with low quiescent current. In addition, 4-bit asynchronous successive approximation register (SAR) ADC which exhibits consumption is employed as quantizer. A delay incorporated into feedback path stable operation of loop. The prototype fabricated in...
This paper presents a 12-bit, 3-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To decrease the number of unit capacitors, hybrid RC digital-to-analog (DAC) is employed. The prototype ADC fabricated with 3.3V devices in an 80nm CMOS process. exhibits differential nonlinearity (DNL) and integral (INL) values that are both less than 0.73 LSB 1.19 LSB, respectively. At 3MHz sampling frequency, attains 67.1dB SNDR 78.6dB SFDR for 0.01MHz input sine wave supply...
This paper presents a second-order discrete-time (DT) delta-sigma (ΔΣ) modulator. A fully passive noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) is employed to increase the noise shaping order without using an additional amplifier, while also performing quantization. The prototype ADC fabricated in 28 nm CMOS process achieves 101.1 dB dynamic range (DR) and 97.6 peak signal-to-noise distortion ratio (SNDR) over signal bandwidth of 500Hz with OSR...
A 430-MS/s 7-b asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a 40 f <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$F$</tex> input sampling capacitor is presented. The proposed ADC reduces the capacitance, which load of buffer amplifier, by separating and array for digital-to-analog (DAC). nonbinary weighted capacitive DAC used to relax settling requirement effect reference fluctuations. prototype...
이 논문은 한국전쟁 초기 대전과 대전에 인접한 지역에서 발생한 교량과 철도 파괴 영상을 통해 대전지역사를 다르게 접근하고 있다. 시기 미군 통신부대는 사진 촬영과 함께 영상 촬영도 담당했다. 영상병은 금강 교량 중 하나인 금남교를 오가는 군병력뿐 아니라, 교량이 폭파되는 장면도 촬영했다. 또한 한국 최초의 임시수도가 되었던 대전의 방어를 앞두고 소개된 대전시가의 모습과 대전시가 전투 당일의 모습, 그리고 대전을 수복한 이후의 파괴된 시가지의 모습까지 고스란히 영상으로 담아냈다. 미군은 방어선 구축을 위해 전투를 폭파를 진행하였지만, 시가지에 대한 파괴는 대부분 전투에서 패한 이후 항공폭격을 진행했다. 철로는 누가 점유하고 있는가에 따라 유용성과 위험성이 교차하는 공통점이 있어 전쟁 파괴의 주된 목표물이 되었다. 과정과 결과로 다수의 민간인이 불의의 희생을 당하는 등 피해가 확산되었지만, 통신부대에서 촬영한 영상에는 직접 담겨 있지 않아 영상의 사각을 이면을 살펴볼 필요가...