A5077512848- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Thin-Film Transistor Technologies
- Ferroelectric and Negative Capacitance Devices
- Nanowire Synthesis and Applications
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Semiconductor materials and interfaces
- Silicon and Solar Cell Technologies
- Silicon Nanostructures and Photoluminescence
- Silicon Carbide Semiconductor Technologies
- MXene and MAX Phase Materials
- Electronic and Structural Properties of Oxides
- Ferroelectric and Piezoelectric Materials
- Advanced Data Storage Technologies
- Photonic and Optical Devices
- ZnO doping and properties
- Copper Interconnects and Reliability
- Force Microscopy Techniques and Applications
- Transition Metal Oxide Nanomaterials
- Cellular Automata and Applications
- Diamond and Carbon-based Materials Research
- 3D IC and TSV technologies
- Advanced ceramic materials synthesis
- Metal and Thin Film Mechanics
National Yang Ming Chiao Tung University
2016-2025
Institute of Electrophysics
2009
National Applied Research Laboratories
1996-2005
National Tsing Hua University
2001
Institute of Electronics
2001
In this letter, we have investigated experimentally, for the first time, feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. situ material features high uniform-doping concentration, facilitating fabrication process. The developed JL device exhibits desirable electrostatic performance in terms higher ON/OFF current ratio...
Microwave annealing (MWA) and rapid thermal (RTA) of dopants in implanted Si are compared their abilities to produce very shallow highly activated junctions. First, arsenic (As), phosphorus (P), <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm BF}_{2}$</tex></formula> implants substrate were annealed by MWA at temperatures below 550 Notation="TeX">$^{\circ}{\rm C}$</tex></formula> . Next,...
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of source drain electrodes CFETs have been overcome by using junctionless transistors, thereby reducing number lithographic steps required. Furthermore, with post metallization treatments, both voltage transfer characteristics (VTCs) butterfly curves SRAM show significant improvements due to symmetry nMOS pMOS...
In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (TSi) was obtained by dry etching wet processes. is controlled etching, the width shrunk down etching. Compared to single nanowire transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For inverter, voltage transfer characteristics (VTCs) could be matched much better...
A low-cost fabrication process of Hf <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{1}-{x}}$ </tex-math></inline-formula> Zr <sub xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> O xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) nonvolatile memory (NVM) was proposed and its characteristics were investigated. We successfully fabricated a ferroelectric tunnel junction (FTJ) device with...
In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices as guard ring material simultaneously fabricated in the same process. High <inline-formula> <tex-math notation="LaTeX">${f}_{\text {T}}$...
In this article, we have demonstrated the utilization of innovative atomic-layer-deposited (ALD) ultrathin ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 1.8 nm) amorphous InSnZnO notation="LaTeX">$\alpha$</tex-math> -ITZO) channel material in development a back-end-of-line (BEOL) compatible thin film transistor (TFT). Through optimization indium/tin/zinc (In/Sn/Zn)...
It has been found that atomic force microscope (AFM) induced local oxidation is an effective way for converting thin (&lt;5 nm) Si3N4 films to SiOx. The threshold voltage the 4.2 nm film as low 5 V and initial growth rate on order of 103 nm/s at 10 V. Micro-Auger analysis selectively oxidized region revealed formation Due large chemical selectivity in various etchants great thermal difference between Si3N4, SiO2, Si, AFM patterning can be a promising method fabricating nanoscale structures.
This paper presents the impacts of an advanced shell doping profile (SDP) on electrical characteristics a junctionless (JL) FET in terms OFF-current, subthreshold swing (SS), and ON-current by numerical simulator. Due to potential mirroring effect, special observation stemming from SDP, carriers can enter intrinsic region doped surface reducing series resistance though junction depth is smaller than 5 nm. The proposed provides additional structure parameter for designing JL showing mitigated...
The high-performance atomic layer deposited (ALD) ultrathin (~2 nm) amorphous InZnO ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${a}$ </tex-math></inline-formula> -IZO, indium: Zinc ≈ 6:4) channel thin-film transistors (TFTs) with a short length notation="LaTeX">$\text{L}_{\mathbf {\textit {ch}}}$ ) of 50 nm were presented. Furthermore, the gate stability was evaluated using temperature-dependent...
In this paper, a comprehensive study of the reliability mechanisms high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with gate dielectric is reported for first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), temperature instability (PBTI), negative-bias (NBS), (NBTI), hot-carrier stress, are used differentiate distribution mechanism trap density states. The generation deep-trap states effective...
For the first time, a novel junctionless (JL) FinFET structure with shell doping profile (SDP) formed by molecular monolayer (MLD) method and microwave annealing (MWA) at low temperature is proposed studied. Thanks to ultra thin SDP leading an easily-depleted channel, JLFinFET can retain ideal subthreshold swing (~ 60 mV/dec) high level according simulations. Poly Si based JLFinFETs processed MLD MWA exhibit superior (S.S. ~ 67mV/dec) excellent on-off ratio (>10 <sup...
In this study, hysteresis-free double-layer gate-all-around stacked poly-Si nanosheet channel ferroelectric Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Zr xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> negative capacitance field-effect transistors (DL GAA NS FE-HZO NC-FETs) with an internal metal gate (IMG) and NH xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma...
Nanometer-scale patterning of TiN films grown on SiO2/Si(001) has been demonstrated using the local electric-field-induced oxidation process with a conductive-probe atomic force microscope. The chemical composition modified region was determined by micro-Auger electron spectroscopy and found to consist Ti, some trace amount N, O, suggesting formation titanium oxynitride in near surface region. dependence oxide height sample bias voltage fixed scanning speed shows nonlinear trend high...
In this letter, 50-nm gate-length nano-silicon-on-insulator FinFETs with deep Ni salicidation and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$hboxNH_3$</tex> plasma treatment are fabricated. It is found that device performances, including subthreshold slope (SS) drain-induced barrier lowering (DIBL) off-state leakage current, can be greatly improved by using process compared to no process. The Ni-salicided devices effectively suppress the...
This research produced high-quality, single-phase nickel titanate (NiTiO3) thin films, a high-k material for gate dielectrics, by modified sol–gel method. The precursor was prepared reactions of acetate tetrahydrate and titanium isopropoxide in 2-methoxyethanol with 1:1 ratio Ni/Ti the solution. After coating, films were post-heat treated between 500° 900°C. X-ray diffraction indicated that deposited at above 600°C titanate. photoelectron spectra typical film revealed binding energies Ni...
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by damage-free conformal molecular monolayer (MLD) method and combination of microwave annealing (MWA) CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> laser spike (COLSA) is demonstrated studied. MWA drives in partially activates the MLD dopants; resultant SDP features an ultra-shallow depth (<; 5nm) abrupt steepness 0.8 nm/dec). The...
For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of 5.3 × 9 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit remarkable I <sub xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> -I...
In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because difference size curvature between planar TG or GAA structures. Because...
We demonstrate that local oxidation of silicon nitride films deposited on conductive substrates with a conductive-probe atomic force microscope (AFM) is very promising approach for nanofabrication. Scanning Auger microscopy and spectroscopy are employed to verify the chemical changes after AFM-induced oxidation. Furthermore, growth kinetics found have logarithmic relationship oxide height versus pulse duration [h∝ln(t/t0)]. In contrast rather slow thermal process, has an anomalously high...
In this letter, high-performance polyimide (PI)-based resistive random access memory (ReRAM) is presented by utilizing a new DAXIN-PI thin film as resistance layer. The switching between highand low-resistance states triggered the formation and dissociation of charge transfer complex. As compared with electrochemical-metallization-based ReRAM valence-change-based ReRAM, shows excellent performance, including large Ron/Roff ratio, superior endurance, low operation voltage, fast speed,...
Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave (MWA) not only shows enhanced FE characteristics but also suppresses leakage interdiffusion compared conventional rapid thermal (RTA). While HZO on Al...