A5091292002- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Copper Interconnects and Reliability
- Nanowire Synthesis and Applications
- Semiconductor materials and interfaces
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Thin-Film Transistor Technologies
- 3D IC and TSV technologies
- Metal and Thin Film Mechanics
- Advanced Surface Polishing Techniques
- Silicon and Solar Cell Technologies
- Diamond and Carbon-based Materials Research
- Mesoporous Materials and Catalysis
- Photonic and Optical Devices
- Carbon Nanotubes in Composites
- Graphene research and applications
- Silicone and Siloxane Chemistry
- Electronic and Structural Properties of Oxides
- MXene and MAX Phase Materials
- GaN-based semiconductor devices and materials
- Anodic Oxide Films and Nanostructures
- Silicon Nanostructures and Photoluminescence
- Electronic Packaging and Soldering Technologies
National Applied Research Laboratories
2011-2024
Taiwan Semiconductor Manufacturing Company (Taiwan)
2019-2024
Hitachi Global Storage Technologies (United States)
2019
National Tsing Hua University
2005-2017
National Yang Ming Chiao Tung University
2005
Motorola (United States)
2003
Horizontally stacked Ge-nanosheet gate-all-around FETs (GAAFETs) are demonstrated for the first time. The Ge/Si multilayers instead of typically used Ge/SiGe ones were epitaxially grown as starting material. To avoid island growth, at a low temperature. Using megasonic agitation, Si in can be easily etched with good selectivity using tetramethylammonium hydroxide water solution an appropriate Finally, p- and n-GAAFETs gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of source drain electrodes CFETs have been overcome by using junctionless transistors, thereby reducing number lithographic steps required. Furthermore, with post metallization treatments, both voltage transfer characteristics (VTCs) butterfly curves SRAM show significant improvements due to symmetry nMOS pMOS...
In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices as guard ring material simultaneously fabricated in the same process. High <inline-formula> <tex-math notation="LaTeX">${f}_{\text {T}}$...
O 2 plasma ashing is commonly used to remove photoresist. The effect of O2 on the porous organosilicate glass (CH3SiO1.5)n, one spin-on materials, investigated. can oxidize methyl groups in (POSG), which leads formation Si–OH groups. hydrophilic will induce moisture uptake so that electrical degradation occur POSG film. Pure hexamethyldisilazane (HMDS) vapor (100% HMDS) react with It converts into hydrophobic Si–O–Si(CH3)3 against uptake. leakage current density decreases by a factor 2–3 and...
For the first time, a novel junctionless (JL) FinFET structure with shell doping profile (SDP) formed by molecular monolayer (MLD) method and microwave annealing (MWA) at low temperature is proposed studied. Thanks to ultra thin SDP leading an easily-depleted channel, JLFinFET can retain ideal subthreshold swing (~ 60 mV/dec) high level according simulations. Poly Si based JLFinFETs processed MLD MWA exhibit superior (S.S. ~ 67mV/dec) excellent on-off ratio (>10 <sup...
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by damage-free conformal molecular monolayer (MLD) method and combination of microwave annealing (MWA) CO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> laser spike (COLSA) is demonstrated studied. MWA drives in partially activates the MLD dopants; resultant SDP features an ultra-shallow depth (<; 5nm) abrupt steepness 0.8 nm/dec). The...
Two parts of work are included in this paper. In the first part, novel Ge gate-all-around field effect transistors (GAA FETs) introduced and discussed. Fabrication GAA FETs requires only simple top-down dry etching blanket epitaxy techniques readily available mass production. First, a process to etch away defective near Ge/Si interface from epitaxial grown on SOI achieves nearly defect-free channel, good gate control triangular gate, larger effective width than rectangular fin, have low...
Abstract In this study, we present a novel Elevated Epitaxy technique that has been developed for the fabrication of single-crystal germanium (Ge) films with (100) orientation, which is ideal monolithic three-dimensional integrated circuits (3D ICs). The crystalline quality and orientation Ge were validated using scanning electron microscopy (SEM), backscatter diffraction (EBSD), transmission (TEM). Additionally, heat transfer dynamics during laser crystallization process analyzed through...
Silver nanoparticles have drawn extensive attention as biomaterial components. Human fibroblasts were grown on various concentrations of silver during the period observation. Normal viability (0% particles) was increased from 6 to 72 hours, increasing amount human (1.5 × 104 7 106 cells/well) normally. Nevertheless, at higher (50%) 1.11 105 cells/well remained after hours. Results indicated that increase in concentration reduced number and affected their fission. found under membranes...
Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave (MWA) not only shows enhanced FE characteristics but also suppresses leakage interdiffusion compared conventional rapid thermal (RTA). While HZO on Al...
We propose a feasible pathway to scale the Ge MOSFET technology by using novel diamond-shaped and <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">09</sub> Si xmlns:xlink="http://www.w3.org/1999/xlink">01</sub> gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching blanket epitaxy techniques readily available in mass production. proposed process involves three...
The interaction between low-k organosilicate glass (OSG) and photoresist removal is investigated. O2 plasma ashing chemical wet stripper are commonly performed to remove (PR) in integrated circuit fabrication. However, or will attack function groups cause Si–OH group formation OSG film during PR processing. often lead moisture uptake consequently dielectric degradation occur film. Trimethylchlorosilane (TMCS) treatment can negate the damage after process. In addition, TMCS react with reduces...
A series of mesoporous silica films with different porosities and pore sizes were prepared using templates or template concentrations in tetraethylorthosilicate colloid solutions. The amphiphilic such as cetyltrimethylammonium bromide (), Brij-56, Tween80, Pluronic P123 used. To investigate the effect self-assembly surfactants on film properties to make a comparison, polyethylene glycol (molecular weight = 1450) which is not surfactant was also used this research. Various porosity,...
A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in silicon gate-all-around nanowire, silicon-oxide-nitride-oxide-silicon (SONOS) can operate at gate voltages of 5 7 V for -7 -9 erasing through Fowler-Nordheim tunneling. The larger voltage is, faster programming/erasing speed wider threshold-voltage shift are attained. Importantly, SONOS cells...
Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> and xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> p- n-NWFETs, respectively, have been achieved by adopting gate-all-around (GAA) configuration. Electrical biasing effects on HZO...
The impact of a realistic representation gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by newly developed thermodynamic energy model based the first principle calculation (FPC). For time, fully couples Landau-Khalatnikov (L-K) equation with grain-size effect in NC-FETs. It explains experimental results phase transition and reveals excellent immunity against depolarization ferroelectric (FE) layer owing to dopant concentration stress thin films. A...
A novel multilevel Schottky barrier nonvolatile nanowire memory is experimentally reported with low-voltage operations and excellent reliability. Using efficient hot-electrons hot-holes generation associated source/drain, the schemes of silicon silicon-oxide-nitride-oxide-silicon (SONOS) cells are achieved at adequately low gate voltages. The n-channel work a small voltage 5 to 7 V using electron programming, whereas p-channel operate -7 -11 hole programming. roles carriers in exchanged...
Ge peaking n- and p-FinFETs have been demonstrated by adopting neutral beam etching (NBE) anisotropic oxidation (NBO) processes. The irradiation-free NB processes not only suppress surface roughness but also guarantee low defect generation on the etched surface. fabricated FinFETs possess several unique features: (1) A fin configuration with a 6-nm top-gate formed an NBO process at room temperature. (2) Nearly defect-free three dimensional channel surfaces (3) Ion Gm improvement as compared...
For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated a layer transfer technique. The 3D channel stacking integration particularly employs low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by surface activating chemical treatment at room temperature, enabling bonded onto wafers. Furthermore, to obtain symmetric performance in n/p FETs, multi-channel structure of two-channel one-channel is also implemented....