A5101721828- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- Digital Filter Design and Implementation
- Advanced Adaptive Filtering Techniques
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Radio Frequency Integrated Circuit Design
- Numerical Methods and Algorithms
- Image and Signal Denoising Methods
- Ferroelectric and Negative Capacitance Devices
- RFID technology advancements
- Electromagnetic Compatibility and Noise Suppression
- Energy Harvesting in Wireless Networks
- Full-Duplex Wireless Communications
- Copper Interconnects and Reliability
- PAPR reduction in OFDM
- Piezoelectric Actuators and Control
- Photonic and Optical Devices
- Iterative Learning Control Systems
- Electronic Packaging and Soldering Technologies
- Rheology and Fluid Dynamics Studies
- Indoor and Outdoor Localization Technologies
- Granular flow and fluidized beds
- Image Processing Techniques and Applications
- Parallel Computing and Optimization Techniques
Harbin Institute of Technology
2025
Taiwan Semiconductor Manufacturing Company (Taiwan)
2004-2024
National Taiwan University of Science and Technology
2012-2024
Feng Chia University
2020
Peking University
2017
Clinical Research Institute
2017
Southern Taiwan Science Park
2014
First Affiliated Hospital of Chinese PLA General Hospital
2013
Huafan University
1999-2005
Case Western Reserve University
1997-1998
For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> high density (HD) SRAM, Cu/low-k interconnect and MiM for mobile SoC computing applications. This provides 2X logic >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To knowledge, this is smallest fully functional 128Mb HD SRAM (with...
For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with smallest high cell of 0.027um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> demonstrated down to 0.5V. The 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup>...
In the Internet-of-Things era, it will be increasingly important to accurately and efficiently locate an object in real world as well identify virtual world. However, is not easy indoor target using radio technology because multipath propagation of waves environment may lead serious position estimation errors. addition, when each has a transceiver or reader operates its high-power mode, overall power consumption whole system considerable. this paper, dual-channel low-power passive RFID...
Advancing the state-of-the-art 16nm technology reported last year, an enhanced CMOS featuring second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin of 450mV achieved with variability reduction for first time. Metal capacitance ∼9% realized...
This paper presents a resource-saving system to extract few important features of electrocardiogram (ECG) signals. In addition, real-time classifiers are proposed as well classify different types arrhythmias via these features. The feature extraction is based on two delta-sigma modulators adopting 250 Hz sampling rate and three wave detection algorithms analyze outputs the modulators. It extracts essential details each heartbeat, encoded into 68 bits data that only 1.48% other comparable...
Previous research results showed that UHF passive CMOS RFID tags had difficulty to achieve sensitivity less than -20 dBm. This paper presents a dual-channel 15-bit tag prototype can work at lower The proposed chip harvests energy and backscatters uplink data 866.4-MHz (for ETSI) or 925-MHz FCC) channel receives downlink 433-MHz channel. Consequently, the transmission does not interrupt our from harvesting RF energy. To use harvested efficiently, we design includes neither regulator nor VCO...
This paper presents a practical method for designing fixed-point FIR filters. The proposed takes both the filter's magnitude response and its hardware cost into consideration in design process. constructs basis set based on coefficients that have been synthesized already. elements are used to synthesize undetermined later. Thus, this expands gradually along with progress of coefficient design. employs some strategies speed up For example, complexity estimation strategy helps us stop digging...
Previous high-performance delay-locked loops (DLLs) were designed in a full-custom design flow that is labor-intensive. Most of those DLLs require tens to hundreds clock cycles achieve synchronization the signal. This paper presents an all-digital DLL (ADDLL) with constant acquisition cell-based flow. The proposed ADDLL circuit can acquire phase signal from 60-MHz frequency 1.2-GHz frequency. In this paper, digitally controlled delay line (DCDL) resettable such our acquisition-cycle...
This paper presents a wide-voltage-range, fast-transient all-digital buck converter using high-resolution digital pulsewidth modulator (DPWM). The employs the multithreshold-voltage band-control technique to shorten its transient response. DPWM uses an delay-locked loop (ADDLL) control cycle. usage of ADDLL leads possessing small area while maintaining high cycle resolution. Moreover, proposed ADDLL-based cyclecontrolled can achieve synchronization between input and output. decreases delay...
For the first time, we demonstrate smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic DIBL of <45mV/V and sub-threshold swing <65mV/decade competitive drive current. Static noise margin ∼90mV operated down to 0.45V is achieved.
The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse selection function. All DCO curves have gentle slopes. selects one before acquisition. To fulfill fast-acquisition requirement, proposed employs phase-frequency-error compensation technique. In acquisition mode, phase-error compensator resolves...
A MASH 111 delta-sigma modulator (DSM) is widely used in a fractional-N frequency synthesizer. This brief presents low-complexity delta-path design by simply recoding all carry output signals from accumulators. Compared with the prior approach, hardware complexity of proposed delta path reduced to 53.4% approach. For synthesizers limited channels or for pipelined DSM accumulators possessing long word lengths, this saving significant.
Stress migration (SM) behavior found on various Cu/Low k interconnects is analyzed in this article. The simulation results demonstrate that the minimum stresses always occur on/near via bottom, which makes dummy insertion an effect way relieving SM induced circuit failure. A numerical index reflecting bulk vacancy density evolution developed from simulated stress distribution and aimed at predicting destination of migrating vacancies driven by thermally generated gradient interconnect...
For the first time, we present a state-of-the-art 32nm low power foundry technology integrated with 0.15um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 6-T high density SRAM, standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is smallest fully functional 2Mb SRAM test-chip node. Low transistors Lg of 30nm achieve current drive 700/380 uA/um at 1.1V off-leakage 1 nA/um...
A passive RFID tag derives its power from RF signal emitted by a reader and responds modulated backscatter signals to the reader. Because of large propagation loss, accessible range is hence limited. In addition, readability often influenced multipath fading problems. order mitigate problems, multi-carrier UHF system utilizes isolated sources which provide additional tags via carrier frequency different with operating frequencies. This approach however affects command demodulation circuit...
A time-to-digital converter (TDC) plays an important role in time interval measurement. Among various TDC structures, the Vernier-based (VTDC) is promising because resolution of it depends on frequency difference between oscillators, not absolute oscillating values. However, oscillators used conventional VTDC require complicated calibration procedures. This makes system complex. paper employs a new soft-injection-locked ring oscillator as clock source for VTDC. The proposed can oscillate...
The distribution of the signed-powers-of-two (SPT) terms canonical signed digit (CSD) numbers is nonuniform. In this paper, author shows an explicit representation distribution. Based on distribution, algorithm proposed for designing fixed-point linear phase FIR filters with CSD coefficients. Design examples demonstrate that can produce using fewer SPT than other methods.
Using a pair of matched square-root-raised-cosine (SRRC) filters in the transmitter and. receiver bandlimited digital communication system can theoretically achieve zero inter-symbol interference (ISI). In reality, such SRRC does not exist. The ISI be only reduced to some level when both are approximately implemented. We propose recursive method design FIR filters. achieved by using resulting SRRC-filter very low while frequency domain specification filter is still maintained. impact clock...