A5074051956- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Advanced Data Storage Technologies
- Distributed and Parallel Computing Systems
- Interconnection Networks and Systems
- Advanced Memory and Neural Computing
- Low-power high-performance VLSI design
- Logic, programming, and type systems
- Cloud Computing and Resource Management
- Ferroelectric and Negative Capacitance Devices
- Advanced Malware Detection Techniques
- Security and Verification in Computing
- Real-Time Systems Scheduling
- Algorithms and Data Compression
- Computer Graphics and Visualization Techniques
- Medical Image Segmentation Techniques
- Software Testing and Debugging Techniques
- Glaucoma and retinal disorders
- Numerical Methods and Algorithms
- Cryptographic Implementations and Security
- Graph Theory and Algorithms
- Experimental Learning in Engineering
- Quantum Computing Algorithms and Architecture
- Advanced Database Systems and Queries
- CCD and CMOS Imaging Sensors
Université Grenoble Alpes
2014-2023
CEA LIST
2012-2023
CEA Grenoble
2014-2023
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2014-2023
Institut polytechnique de Grenoble
1992-2019
CEA LETI
1992-2019
Kwame Nkrumah University of Science and Technology
2017
CEA Cadarache
2017
Direction de la Recherche Technologique
2014-2016
Integra (United States)
2013
Energy consumption is the major factor limiting performance in embedded systems. In addition, next generations of ICs, heat or energy constraints will not allow to power all transistors simultaneously. Heterogeneous multicore systems represent a possible solution this problem: diversity cores provides and trade-offs.
Heterogeneous multicore systems have gained momentum, specially for embedded applications, thanks to the performance and energy consumption trade-offs provided by inorder out-of-order cores. Micro-architectural simulation models behavior of pipeline structures caches with configurable parameters. This level abstraction is well known being flexible enough quickly evaluate new hardware implementations, such as future heterogeneous platforms. However, currently, there no open-source...
This paper presents a novel energy-efficient and Dynamically Reconfigurable Computing Circuit (DRC <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) concept based on memory architecture for data-intensive (imaging, ...) secure (cryptography, applications. The proposed computing circuit is 10-Transistor (10T) 3-Port SRAM bitcell array driven by peripheral circuitry enabling all basic operations that can be traditionally performed an ALU....
Modern computing applications require more and data to be processed. Unfortunately, the trend in memory technologies does not scale as fast performances, leading so called wall. New architectures are currently explored solve this issue, for both embedded off-chip memories. Recent techniques that bringing close possible array such as, In-Memory Computing (IMC), Near-Memory (NMC), Processing-In-Memory (PIM), allow reduce cost of movement between cores For computing, scheme presents...
We present an approach and a tool to answer the need for effective, generic, easily applicable protections against side-channel attacks. The protection mechanism is based on code polymorphism, so that observable behaviour of protected component variable unpredictable attacker. Our combines lightweight specialized runtime generation with optimization capabilities static compilation. It extensively configurable. Experimental results show programs secured by our strong security levels meet...
• A 24-year-old woman was seen with painless, progressive, unilateral visual acuity loss, optic nerve swelling, and opticociliary shunt vessels. Results of a skull series conventional tomography showed enlargement erosion the canal. In addition, computed (CT) disclosed thickened consistent sheath meningioma. preoperative diagnosis granulomatous neuropathy based on presence mild posterior uveitis, "snowball" opacities in vitreous ("string pearl" sign), slightly elevated angiotensin-converting...
In the context of highly data-centric applications, close reconciliation computation and storage should significantly reduce energy-consuming process data movement. This letter proposes a computational SRAM (C-SRAM) combining in- near-memory computing (IMC/NMC) approaches to be used by scalar processor as an energy-efficient vector processing unit. Parallel is thus performed on vectorized integer large words using usual logic arithmetic operators. Furthermore, multiple rows can...
In-memory computing (IMC) aims at solving the performance gap between CPU and memories introduced by memory wall. However, general-purpose IMC does not consider optimization of data transfers for patterns, such as stencils convolutions. This article proposes a new instruction set architecture (ISA) novel pattern encoding to transfer organize streams in order perform efficiently computation. is implemented on data-locality management unit (DMU) subset computational SRAM (C-SRAM) ISA. A...
The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes brains, harnesses the latest advances <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{33D}$</tex> stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently accurately runs computer vision algorithms area-constrained endpoint chips. rationale behind is:...
This paper presents the computing model for InMemory Computing architecture based on SRAM memory that embeds abilities. concept offers significant performance gains in terms of energy consumption and execution time. To handle interaction between CPU, new instruction codes were designed. These instructions are communicated by CPU to memory, using standard buses. implementation allows (1) embed In-Memory capabilities a system without Instruction Set Architecture (ISA) modification, (2) finely...
The advent of portable software-defined radio ( sdr ) technology is tightly linked to the resolution a difficult problem: efficient compilation signal processing applications on embedded computing devices. Modern wireless communication protocols use packet rather than infinite stream and also introduce dependencies between data value computation behavior leading dynamic dataflow behavior. Recently, parametric has been proposed support dynamicity while maintaining high level analyzability...
This article presents Computational SRAM (C-SRAM) solution combining In- and Near-Memory Computing approaches. It allows performing arithmetic, logic, complex memory operations inside or next to the without transferring data over system bus, leading significant energy reduction. Operations are performed on large vectors of occupying entire physical row C-SRAM array, high performance gains. We introduce in this as an integrated vector processing unit be used by a scalar processor...
Efficient programming of signal processing applications on embedded systems is a complex problem. High level models such as Synchronous dataflow (SDF) have been privileged candidates for dealing with this complexity. These permit to express inherent application parallelism, well analysis both verification and optimization. Parametric aim at providing sufficient dynamicity model new applications, while the same time maintaining high analyzability needed efficient real life implementations.
For big data applications, bringing computation to the memory is expected reduce drastically transfers, which can be done using recent concepts of Computing-In-Memory (CIM). To address kernels with larger sets, we propose a reconfigurable tile-based architecture composed Computational-SRAM (C-SRAM) tiles, each enabling arithmetic and logic operations within memory. The proposed horizontal scalability vertical communication are combined select optimal vector width for maximum performance....
Wavelet denoising of medical images relies on the technique thresholding.A disadvantage this method is that even though it adequately removes noise in an image, introduces unwanted artifacts into image near discontinuities due to Gibbs phenomenon.A total variation for enhancing chest radiographs implemented.The approach focuses lung nodules detection using (CRs) and achieves high sensitivity could reduce average number false positives radiologists encounter.
This paper presents a new methodology for automating the Computational SRAM (C-SRAM) design based on off-the-shelf memory compilers and configurable RTL IP. The main goal is to drastically reduce development effort compared full-custom design, while offering flexibility of use high-yield production. proposed C-SRAM architecture has been developed process energy-efficient vector data coupled with scalar processor, limiting transfer system bus. results obtained by post P&R simulations show...
General purpose CPUs used in high performance computing (HPC) support a vector instruction set and an out-of-order engine dedicated to increase the level parallelism. Hence, related optimizations are currently critical improve of applications requiring numerical computation. Moreover, use Java run-time environment such as HotSpot Virtual Machine (JVM) is promising alternative. It benefits from its programming flexibility, productivity ensured by Just-In-Time (JIT) compiler. Though, JIT...