A5102854602- High-Energy Particle Collisions Research
- Particle physics theoretical and experimental studies
- Quantum Chromodynamics and Particle Interactions
- Particle Detector Development and Performance
- Nuclear reactor physics and engineering
- Radiation Detection and Scintillator Technologies
- Atomic and Subatomic Physics Research
- Advanced Data Storage Technologies
- Cosmology and Gravitation Theories
- Dark Matter and Cosmic Phenomena
- Nuclear physics research studies
- Statistical Methods and Bayesian Inference
- CCD and CMOS Imaging Sensors
- Pulsars and Gravitational Waves Research
- Stochastic processes and statistical mechanics
- Computational Physics and Python Applications
- Electromagnetic Scattering and Analysis
- Superconducting Materials and Applications
- Algorithms and Data Compression
- Distributed and Parallel Computing Systems
- Muon and positron interactions and applications
- Statistical Mechanics and Entropy
- Radiation Effects in Electronics
- Black Holes and Theoretical Physics
- Advancements in Semiconductor Devices and Circuit Design
University of South-Eastern Norway
2014-2025
A. Alikhanyan National Laboratory
2015-2024
University of Pavol Jozef Šafárik
2023-2024
University of Bergen
2006-2024
Sewanee: The University of the South
2013-2021
Vestfold University College
2013-2019
Lund University
2018
European Organization for Nuclear Research
2012-2013
Czech Technical University in Prague
2012
Bergen Community College
2004
In this paper we present the front end electronics for time projection chamber (TPC) of ALICE experiment. The system, which consists about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates shaping-amplifier circuits 16 channels; (b) a mixed-signal (ALTRO) integrates each consisting 10-bit 25-MSPS ADC, baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. complete readout chain contained in cards (FEC), with 128...
The front end electronics for the ALICE time projection chamber (TPC) consists of about 560000 channels packed in 128-channel units (front card). Every card (FEC) incorporates circuits to amplify, shape, digitize, process and buffer TPC pad signals. From control readout point view FECs are organized 216 partitions, each being an independent system steered by one unit (RCU). RCU, which is physically part on-detector electronics, implements interface data acquisition (DAQ), trigger timing...
This paper presents the solution for optimization of ALICE TPC readout running at full energy in Run2 period after 2014. For data taking with heavy ion beams an event rate 400 Hz a low dead time is envisaged central barrel detectors during these three years. A new component, Readout Control Unit 2 (RCU2), being designed to increase present by factor up 2.6. The immunity radiation induced errors will also be significantly improved design.
The first results on fully corrected ratios and production cross sections of ??, , ?? detected by the WA97 experiment in Pb - collisions are presented.
The readout electronics for the ALICE TPC detector consists of 4356 front-end cards (FECs) that contain complete chain to signals coming from 570132 pads. are grouped in 216 partitions, each controlled by a Readout Control Unit (RCU) interfaces FECs DAQ, Trigger, and Detector System. RCU broadcast trigger information FECs, collects related data assembles sub-event, compresses sends compressed packed sub-event DAQ via Data Link (DDL). is designed cope with maximum throughput 200 Mbyte/s. In...
This paper addresses the performance of Front End Card (FEC) for ALICE Time Projection Chamber (TPC) on measured data. The TPC Electronics consists 557568 channels. A single readout channel is made two basic units: (a) an analogue ASIC (PASA) that incorporates shaping/amplifier circuits 16 channels; (b) a mixed-signal (ALTRO) integrates channels, each consisting 10-bit 25-MSPS ADC, baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. complete chain...
Functionality and flexibility has been significantly enhanced with this novel sea of modules FPGA architecture. It includes a new improved logic cell, high performance interconnect architecture full featured fracturable flip flops. The is designed for in system as well low cost user programmable implementations. A flexible I/O complements the input/output delays. modular design methodology allows quick proliferation to multiple families while tailoring individual family characteristics...