A first-step half-reference ramping (FHR) readout scheme is presented in this study for high frame rate CMOS image sensors (CISs). The proposed enhances the conversion speed of a single-slope (SS) analog-to-digital converter (ADC) by applying binary-weighted searching algorithm at first A/D attempt. By effectively reducing reference signal range, FHR can reduce number steps SS ADC while maintaining performance. Furthermore, reversible to operate conventional algorithm, thus it preserves...

This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the properties. The proposed delta-readout (A-readout) reads signal difference between two pixels located next to each other (Apixel) by utilizing most significant bits (MSBs) information of previous pixel. By effectively reducing dynamic range signal, compensated A-window checking, A-readout can reduce effective number decision cycles in successive-approximation register (SAR) analog-to-digital...

This article presents a real-time edge image extraction CMOS sensor (CIS) with an edge-detection counter for machine vision applications. By examining conventional column-parallel (CP) CIS imaging structure single-slope analog-to-digital convertor (SS ADC), it discovered additional time slot available to extract information of during normal operation two adjacent columns. While obtaining in this study, the prototype proposed effectively utilizes spare extracting column without signal...

This study presents a CMOS image sensor (CIS) with two-step single-slope (TS-SS) analog-to-digital convertor (ADC), wherein the differential topology characteristics of ramp generator are used. The proposed TS-SS ADC effectively resolves 1 most significant bit (MSB) half-ramping full (A/D) reference at coarse conversion and remaining least bits (LSBs) slope ramping signals from generator. readout scheme maintains existing column structure does not require to regenerate coarse-step region in...

This paper presents a CMOS image sensor (CIS) utilizing noise-shaping successive-approximation register analog-to-digital converter (SAR ADC) incorporating the delta-readout scheme. While SAR ADC with proposed two-tap passive finite-impulse response (FIR) filter improves effective resolution, scheme reduces its power consumption. A prototype <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1920\times 1440$...

Based on an analysis of the signal characteristics gas sensors, this work presents a chemoresistive sensor readout circuit design for detecting gases with slow response time characteristics. The proposed directly generates reference voltage corresponding to initial value and extracts only amount concentration change in sensor. Because can adaptively regenerate suitable under various changing ambient conditions, it alleviate variation output values at same caused by non-uniformities among...

This study proposes a chemoresistive gas sensor readout integrated circuit (ROIC) with simple and effective scheme for tracking canceling the offset value. Before reading out sensor, proposed ROIC dynamically updates of analog-to-digital (A/D) reference range suitable to offset, enabling accurate A/D conversion within sensor's dynamic (DR). Therefore, this approach eliminates need additional complex circuitry or compensation algorithms, allowing extract desired amount change effectively. As...

This paper presents a CMOS image sensor (CIS) that extracts multi-level edge as well human-friendly normal in real time from conventional pixels for machine-vision applications, utilizing proposed speed/power efficient dual-mode successive-approximation register analog-todigital converter (SAR ADC). The readout scheme operates two modes, fine step SAR (FS-SAR) mode and coarsestep single-slope (CS-SS) mode, depending on the difference (A) between chosen pixel previous pixel. If is at boundary...

This study introduces a readout integrated circuit (ROIC) tailored for multi-gas sensor arrays featuring proposed baseline calibration scheme aimed at mitigating the issue of variation. Unlike previous approaches, stores each sensor’s value and dynamically updates signal extraction range accordingly during ROIC operation. adjustment allows optimal use ROIC’s dynamic range, enhancing uniformity accuracy without need complex additional circuitry or advanced post-processing algorithms. We...

This article presents a black-sun readout scheme for CMOS image sensors (CISs) that utilizes the effect caused by strong illumination condition. Based on analysis of phenomenon in CISs, proposed CIS extracts indication and its strength images while providing normal without any degradation. By effectively utilizing capability, prototype with was identified as useful solution to track brightest source light. In addition, is reversible conventional such it can be used various purposes several...

This paper proposes a low-power logarithmic resistance sensor for multi-level cell phase-change memory readout. The proposed is composed of resistance-to-current converter (R2I) and current-to-digital (I2D). A simple bleeding current source pair added to the R2I enhances settling speed sensing accuracy. two-step I2D with time-to-digital converter-configured fine ADC could be designed consumption small size owing time-reference generator that shared by multiple channels incorporates...

Abstract This letter presents a wide dynamic range (WDR) feature extraction (FE) readout scheme for machine vision applications using CMOS image sensors (CISs). The proposed with the pixel structure has two operating modes, normal and WDR modes. In mode, CIS captures high sensitivity. addition, as unique function, bi‐level is obtained real‐time FE even if saturated in strong illumination conditions. Thus, compared to typical CISs vison, can reveal object features that are blocked by light...

This paper presents a low-power multiple-column-parallel (MCP) readout CMOS image sensor (CIS) in terms of its structural features. Because each column an MCP unit performs analog-to-digital (A/D) conversion sequentially, the columns have their own operating periods before and after A/D conversion. Upon completion column, local bias control (LBC) scheme is applied using circuit pixel source follower (SF) to minimize power consumption. In this study, effectiveness proposed LBC verified for...

This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields 15 μm-width compact single channel column parallel structure. current-mode 2 flash coarse conversion and the pipelined between enhance rate up to 13 Mcells/sec. With enhanced residue accuracy provided by replica generator, achieves excellent linearity 9.96 b (linear equivalent). The...

A compact two-step 5b logarithmic ADC is designed for the readout application of multi-level cell phase-change memory (PCM). bleeding-current-assisted regulated-cascode stage accurately converts wide-dynamic range resistance a PCM into current. The composed 2b current-mode flash as coarse and 3b time-to-digital converter fine with redundancy, resulting in size low power consumption. minimum step-size 0.1% full scale conversion time 100 ns. chip was fabricated 65 nm CMOS width single channel...

We present an AC-coupled modular 16-channel analog frontend with 1.774 fJ/c-s∙mm2 energy- and area-product for a multichannel recording of broadband neural signals including local field potentials (LFPs) extracellular action (EAPs). To achieve such small area- energy-product, we employed operational transconductance amplifier (OTA) positive feedback, instead widely-used folded cascode OTA (FC-OTA) or current mirror conventional recordings, while optimizing the design parameters affecting...

A power-saving readout scheme for CMOS image sensors (CIS) that utilizes the properties is presented. The proposed delta-readout (Δ-readout) reads signal difference between two pixels located next to each other. By effectively reducing dynamic range of signal, ADC can reduce number decision cycles and save power consumption while maintaining performance at level a conventional ADC. prototype QQVGA CIS with ten 10-bit SAR ADCs in multi-column-parallel (MCP) configuration was fabricated 1P4M...

In the treatment of septic patients, prediction a pathogen's susceptibility to piperacillin-tazobactam can be crucial. Commercial tests are available measure piperacillin-tazobactam, but there is conflicting evidence regarding their accuracy. Therefore, this study compared accuracy disk diffusion, gradient strip, and automated dilution with accepted standard broth microdilution. Testing was performed on 150 blood culture isolates from hospitalized patients at University Hospital Bonn. The...

Abstract A new readout circuit architecture for capacitive touch screen panels (TSPs) is introduced to enhance the reporting rate and improve signal noise ratio (SNR) with low power consumption. The proposed Dual‐Mode Sensing (DMS) method finds actual spots without feedback from TSP MCU. In addition, effect of coupled reduced owing averaging continuous‐time integration (CTI) technique. was designed a 0.35 μm CMOS technology. sensing scheme shows 257 Hz under simultaneous 10 condition on 10.1...