A5066065488- Advanced Memory and Neural Computing
- Analog and Mixed-Signal Circuit Design
- CCD and CMOS Imaging Sensors
- Phase-change materials and chalcogenides
- Low-power high-performance VLSI design
- Semiconductor materials and devices
- Image Processing Techniques and Applications
- Advancements in Semiconductor Devices and Circuit Design
- Infrared Target Detection Methodologies
- Thin-Film Transistor Technologies
Korea Advanced Institute of Science and Technology
2014-2018
Yuhan University
2015
This paper presents an asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC as a suitable architecture in low-supply-voltage condition. Settling-While-Conversion enabled by the Assist-ADC relaxes DAC settling time requirement and makes it possible to insert minimized capacitor shuffling logic with no speed penalty. A proposed gain-boosting dynamic pre-amplifier enhances noise performance of comparator self time-reference generation function is embedded for speed-enhanced decision....
This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the properties. The proposed delta-readout (A-readout) reads signal difference between two pixels located next to each other (Apixel) by utilizing most significant bits (MSBs) information of previous pixel. By effectively reducing dynamic range signal, compensated A-window checking, A-readout can reduce effective number decision cycles in successive-approximation register (SAR) analog-to-digital...
This paper presents a CMOS image sensor (CIS) utilizing noise-shaping successive-approximation register analog-to-digital converter (SAR ADC) incorporating the delta-readout scheme. While SAR ADC with proposed two-tap passive finite-impulse response (FIR) filter improves effective resolution, scheme reduces its power consumption. A prototype <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1920\times 1440$...
This paper presents a CMOS image sensor (CIS) that extracts multi-level edge as well human-friendly normal in real time from conventional pixels for machine-vision applications, utilizing proposed speed/power efficient dual-mode successive-approximation register analog-todigital converter (SAR ADC). The readout scheme operates two modes, fine step SAR (FS-SAR) mode and coarsestep single-slope (CS-SS) mode, depending on the difference (A) between chosen pixel previous pixel. If is at boundary...
This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) bio-potential signal acquisition: skip-reset, delta ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta$ </tex-math></inline-formula> ) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but also...
This paper proposes a low-power logarithmic resistance sensor for multi-level cell phase-change memory readout. The proposed is composed of resistance-to-current converter (R2I) and current-to-digital (I2D). A simple bleeding current source pair added to the R2I enhances settling speed sensing accuracy. two-step I2D with time-to-digital converter-configured fine ADC could be designed consumption small size owing time-reference generator that shared by multiple channels incorporates...
This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields 15 μm-width compact single channel column parallel structure. current-mode 2 flash coarse conversion and the pipelined between enhance rate up to 13 Mcells/sec. With enhanced residue accuracy provided by replica generator, achieves excellent linearity 9.96 b (linear equivalent). The...
A compact two-step 5b logarithmic ADC is designed for the readout application of multi-level cell phase-change memory (PCM). bleeding-current-assisted regulated-cascode stage accurately converts wide-dynamic range resistance a PCM into current. The composed 2b current-mode flash as coarse and 3b time-to-digital converter fine with redundancy, resulting in size low power consumption. minimum step-size 0.1% full scale conversion time 100 ns. chip was fabricated 65 nm CMOS width single channel...
A power-saving readout scheme for CMOS image sensors (CIS) that utilizes the properties is presented. The proposed delta-readout (Δ-readout) reads signal difference between two pixels located next to each other. By effectively reducing dynamic range of signal, ADC can reduce number decision cycles and save power consumption while maintaining performance at level a conventional ADC. prototype QQVGA CIS with ten 10-bit SAR ADCs in multi-column-parallel (MCP) configuration was fabricated 1P4M...