ABSTRACT In this Letter, we propose a novel current‐mirror‐based lossless integration stage. The proposed stage is derived from the lossy counterpart by simply incorporating an additional DC current source. unique offered contribution reduction of circuit complexity in resulting current‐mode systems, where introduced integrator utilized. This verified through performed comparison with corresponding stage, which already literature. A multiple‐output biquad filter designed using integrator,...

Fractional-Order circuits and networks being a widely researched field lags in its development due to the non-availability of basic building block i.e. Element (FOE). The FOE besides compact having wide frequency range should also be integrable with Integrated Circuit (IC). In this paper, detailed survey single multi-component implementations has been carried out. implies that component is more suited for integration conventional circuitry but market fit device still topic research. Some...

A fully integrated implementation of a parallel fractional-order resonator that employs together capacitor and inductor is proposed in this brief. The design utilizes current-controlled operational transconductance amplifiers as building blocks, designed, fabricated AMS 0.35-μm CMOS process based on second-order approximation differentiator/integrator magnitude optimized the range 10 Hz-700 Hz. An attractive benefit scheme its electronic tuning capability.

Summary Novel topologies of fractional‐order generalized filters are introduced in this paper. These offer the following benefits: (1) realization lowpass, highpass, bandpass, allpass, or bandstop filter functions by same topology; (2) resistorless realizations; (3) electronic adjustment their frequency characteristics as well order; and (4) employment only grounded capacitors. All above have been achieved using Operational Transconductance Amplifiers active elements appropriate...

Due to the absence of commercially available fractional-order capacitors and inductors, their implementation can be performed using differentiators integrators, respectively, combined with a voltage-to-current conversion stage. The transfer function integrators approximated through utilization appropriate integer-order functions. In order achieve that, Continued Fraction Expansion as well Oustaloup’s approximations utilized. accuracy, in terms magnitude phase response, functions...

This paper presents the design and implementation of fractional-order filters based on promising CMOS structure Differential Difference Current Conveyor (DDCC), which was designed fabricated using 0.35 μm AMIS process. The derivation has been achieved a second-order approximation corresponding transfer functions. offer benefit low-voltage (±500 mV) operation as well requirement grounded passive elements. In addition, technique for quick high-order introduced. simulation experimental results...

The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. chip contains capacitors orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through bias current. Two off-chip used to set the bandwidth each emulator independently. was designed in Austria microsystems (AMS) 0.35μ CMOS.

A new approximation method of the fractional-order Laplacian operator s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">α</sup> is introduced. The based on a weighted sum first-order filter sections and its analytical proof given. optimal high-pass section parameters that cover six frequency decades are obtained using flower pollination algorithm while effect number accuracy investigated. Approximations capacitors orders α = 0.5 0.7 synthesized...

Summary Novel configurations of fractional‐order filter topologies, realized through the employment concept companding filtering, are introduced in this paper. As a first step, design procedure is presented systematic algorithmic way, while next basic building blocks sinh‐domain and log‐domain integrators presented. Because metal–oxide–semiconductor (MOS) transistors operated subthreshold region, derived structures offer capability for operation an ultra‐low‐voltage environment. In addition,...

The low-voltage low-power sinh-domain (SD) implementations of integer- and fractional-order FitzHugh-Nagumo (FHN) neuron model have been introduced in this paper. Besides, the effect fractional-orders on external excitation current dynamics has examined proposed SD designs FHN benefits of: 1) operation; 2) integrability, due to resistor-less design employment only grounded components; 3) electronic tunability performance parameters; 4) implementation inherent properties technique. HSPICE...

Summary Fractional‐order blocks, including differentiators, lossy and lossless integrators as well filters of order 1 + a (0 &lt; 1), are presented in this paper. The proposed topologies offer the benefit ultra low‐voltage operation; addition, reduced circuit complexity is achieved compared to corresponding companding schemes, which have been already introduced literature. ultra‐low voltage operation performed through employment metal oxide semiconductor transistors biased subthreshold...

Summary Approximations of the fractional‐order differentiator and integrator operators s ± r are proposed in this work. These approximations target realization these using standard active filter transfer functions. Hence, circuit implementations integrated form or discrete component significantly facilitated. Complementary metal‐oxide‐semiconductor (CMOS) realizations given validated via simulations AMS 0.35 μm CMOS technology, while experimental results operational amplifier circuits tested...

Higher-order fractional filters with fully controllable frequency characteristics are realized in this work, after fitting the filter's magnitude response data using a minimum-phase state-space model. Subsequently, rational integer-order transfer functions derived and implemented as active elements: a) Operational Transconductance Amplifiers (OTAs) b) Field Programmable Analog Array (FPAA) device. The enjoy electronic adjustability of their type, order, characteristic frequencies while being...

Fractional-order Butterworth filters of order 1 + α (0 &lt; 1) can be implemented by a unified structure, using the method presented in this paper. The main offered benefit is that cutoff frequencies are fully controllable very simple and, also, various types (e.g., low-pass, high-pass, band-pass, and band-stop) could realized. Thanks to employment Field Programmable Analog Array device, implementation introduced reconfigurable, sense filter functions as well their both programmable.

A novel kind of non-integer order bilinear filters, named double-order is introduced in this work. They are based on the employment two orders, offering maximum design flexibility comparison with their fractional-order and power-law counterparts. An attractive offered benefit that achieved without increasing circuit complexity, since proposed structure capable realizing all kinds filters. Two examples provided, where it shown lead/lag compensators utilized control applications low/high...

A study of the behavior power-law negative group delay filters, accompanied by a comparison with their integer-order counterparts, is performed in this work. Employing curve-fitting based approximation technique, resulting rational transfer function versatile sense that it has same form independent order and/or type filter. Its implementation following three alternative approaches, each one offering different advantages. The findings work are supported simulation and experimental results...

Abstract A theoretical study of the behavior some elementary first- and second-order functions, which are suitable for realizing negative group delay, is performed in this work. As both gain phase responses simultaneously considered, important derivations related to actual bandwidth operation derived accompanied by useful design tips. The presented theory supported simulation experimental results obtained through utilization typical active-RC filter structures, as well from a...

Summary We propose a family of equal‐R equal‐C dual amplifier oscillators with gain‐tunable start‐up condition and oscillation frequency. In particular, while one the amplifiers can be used to satisfy oscillator condition, second tune this regard, it is observed that frequency made very low or high independent RC time constant circuit by properly choosing gain topology. possible topology, directly proportional tuning gain, in inversely gain. Both topologies generate two outputs which also...