A5069238230- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Low-power high-performance VLSI design
- CCD and CMOS Imaging Sensors
- Sensor Technology and Measurement Systems
- Advanced MEMS and NEMS Technologies
- Neural Networks and Applications
- VLSI and Analog Circuit Testing
- Photonic and Optical Devices
- Neuroscience and Neural Engineering
- Advanced Sensor Technologies Research
- Semiconductor materials and devices
- Semiconductor Lasers and Optical Devices
- Digital Filter Design and Implementation
- Electromagnetic Compatibility and Noise Suppression
- Advanced Battery Technologies Research
- Innovative Energy Harvesting Technologies
- Blind Source Separation Techniques
- Advanced Fiber Laser Technologies
- Acoustic Wave Resonator Technologies
- Microwave Engineering and Waveguides
- Electrostatic Discharge in Electronics
- Numerical Methods and Algorithms
University of Patras
2015-2024
Aristotle University of Thessaloniki
1998-2003
A new experiment is described to detect a permanent electric dipole moment of the proton with sensitivity $10^{-29}e\cdot$cm by using polarized "magic" momentum $0.7$~GeV/c protons in an all-electric storage ring. Systematic errors relevant are discussed and techniques address them presented. The measurement sensitive physics beyond Standard Model at scale 3000~TeV.
This paper introduces the novel design of a low-voltage low-power voltage rectifier based on bulk-driven (BD) winner-take-all (WTA) circuit. The proposed circuit is able to work as half- or full-wave and it specifically designed for battery-powered implantable wearable medical devices. main attractive features are topology simplicity, minimal number transistors, accuracy capability rectifying signals with relatively wide range frequencies amplitudes. was single supply 0.6 V consumes about...
Abstract A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It based on a partial positive feedback and offers significant improvement of both transconductance noise performance compared with those achieved by the corresponding already published structures. The also extended common‐mode range under low supply voltage relevant to gate‐driven differential pair. amplifier designed, which includes an auxiliary for output stabilization latch‐up...
A current-mode analogue circuit that implements a pseudo-exponential function is proposed. The design of the based on Taylor's series approximation, using MOS transistors in saturation region. advantages this output current presents very low temperature coefficient (TC) and also immune to body-effect. Simulation experimental results show offers maximum range ~30 dB, with an error less than 1 dB TC = –233 ppm/°C.
A new systematic design procedure for square-root-domain (/spl radic/x-domain) circuits, which is based on the signal flow graph (SFG) synthesis approach, introduced in this paper. The SFG of prototype system modified, using a proposed set operators, such way that /spl radic/x-domain building blocks could be used corresponding implementations. For purpose, integrator circuits have been were constructed from current-mode geometric-mean and multiplier/divider circuits. main advantages are...
A new differential voltage follower based on bulk-driven transistors is presented. The constant gain with value close to unity, input common-mode suppression and rail-to-rail operation are the most important advantages of proposed structure. can be used as stage a gate-driven pair stabilising its gate-transconductance for range. circuit was designed tested using standard 0.18 µm CMOS process 1V supply voltage.
This paper presents a new CMOS structure for fully balanced differential difference amplifier (FB-DDA) designed to operate from sub-volt supply. employs the bulk-driven quasi-floating-gate (BD-QFG) technique achieve capability of an ultra-low voltage operation and extended input range. The proposed BD-QFG FB-DDA is suitable ultra-low-voltage low-power applications. circuit with single supply 0.5 V consumes only 357 nW power. was simulated in 0.18-μm TSMC technology simulation results prove...
This paper proposes a VCO which is based on pseudo-differential ring oscillator scheme and it suitable for multi-Gbps serial interfaces. The topology two CMOS inverters loaded by simple negative resistance realized with pMOS transistors. circuit performance compliant the MIPI Alliance M-PHY standard most updated high-speed interface technology. designed simulated in 65nm process 1.2 V supply voltage. frequency tuning range was 1.9 to 3.5 GHz an almost constant K <sub...
In this paper, it is proposed a jitter analysis methodology, targeting on the optimization of phase interpolator (PI) based clock and data recovery circuit (CDR). The methodology applied for optimized design an 8-bit dual-loop CDR, designed with CMOS TSMC 65 nm process node. CDR extended, in terms resolution, version, novel PI topology work. loop has minimum frequency offset tracking ability equal to 500ppm at 5.83 Gbps, so suitable adoption either mesochronous or plesiochronous High Speed...
In this brief, a very simple differential voltage attenuator based on floating-gate MOS transistors (FGMOS) is proposed. The constructed by only two stacked identical FGMOS in saturation region, provides output proportional to the difference of input voltages. advantages are low supply operation, rail-to-rail range with small linearity error and single-ended processing. A efficient technique transform any circuit that requires balanced inputs into counterpart attenuator, Using technique,...
In this paper, we present voltage-mode and current-mode computational circuits using floating-gate MOS (FGMOS) transistors, operating in saturation region. The are designed two FGMOS basic-cells, each one formed by three transistors with common source. first basic cell is connected voltage mode, while the second configuration order to implement circuits, respectively. Using cells, current squarers, four-quadrant multipliers a square rooter designed. Mismatches distortion analysis for...
SUMMARY A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a bulk‐driven voltage follower with conventional gate‐driven amplification stages. presents gain equal to unity while suppressing the input common‐mode voltage. operates at supply of less than 0.5 V, performing transconductance almost gate and relatively high without need for boosting. circuit was designed simulated using standard 0.18‐µm CMOS n ‐well process. low‐frequency 56 dB,...
A high-accuracy voltage reference generator is proposed in this paper. It has been designed a CMOS 65 nm technology node, operating with typical supply of 1.2 V, which provides equal to 0.5 V. Measurement results the fabricated chip show variation less than 0.04% over temperature range from −40 125 °C and 0.9% corners. The design demonstrates low noise output good performance under mismatch. current included provide constant current. measured about 1%.
This paper presents a novel circuit of z−1 operation which is suitable, as basic building block, for time-domain topologies and signal processing. The proposed employs time register based on the capacitor discharging method. large variation slope over technology process chip temperature variations affect accuracy improved using digital calibration loop. designed 28 nm Samsung FD-SOI under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate theoretical analysis...
This paper presents the hardware implementation of a 3rd-order low-pass finite impulse response (FIR) filter based on time-mode signal processing circuits. The topology consists set novel building blocks that perform necessary functions in including z−1 operation, time addition and multiplication. proposed FIR was designed 28 nm Samsung fully-depleted silicon-on-insulator FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate theoretical analysis....
A simple squarer based on floating-gate MOS transistors is presented. The has rail-to-rail input range with less than 0.5% non-linearity error. Using this single-ended and/or differential signals can be processed without additional circuitry. Also, a four quadrant analogue multiplier realised using the proposed squarer. Simulation results are given to verify theoretical analysis.
A simple automatic tuning circuit is proposed which suitable for controlling very large channel resistance of weak‐inverted transistors operated in the linear regime. The 1.2 MΩ nominal value presents about ± 0.6% variation −20–80°C temperature range, ±5% at process/temperature (P/T) corners and total harmonic distortion = −42 dB differential signals. supply voltage was V DD 1 current consumption 470 nA. concept performance were confirmed evaluated by simulations using standard 0.35 μm CMOS process.