This paper presents a novel circuit of z−1 operation which is suitable, as basic building block, for time-domain topologies and signal processing. The proposed employs time register based on the capacitor discharging method. large variation slope over technology process chip temperature variations affect accuracy improved using digital calibration loop. designed 28 nm Samsung FD-SOI under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate theoretical analysis...

This paper presents the hardware implementation of a 3rd-order low-pass finite impulse response (FIR) filter based on time-mode signal processing circuits. The topology consists set novel building blocks that perform necessary functions in including z−1 operation, time addition and multiplication. proposed FIR was designed 28 nm Samsung fully-depleted silicon-on-insulator FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency. Simulation results validate theoretical analysis....

In this work, a discrete-time feedforward comb filter suitable for time-mode signal processing (TMSP) is proposed. The frequency response of the proposed digitally programmable. Both input and output system are synchronous with sampling signal, which also characterized by modular hierarchical design. As result, can be used as building block implementation higher-order systems. was designed verified in TSMC 65nm technology process. rate 5MHz, voltage supply 1.2V, consuming 540gW use 9 unit delay taps.

Time-mode signal processing is an advantageous approach in which the time variable. Time register used construction of time-mode z <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> operator basic building block circuits and systems such as FIR/IIR filters amplifiers implementations. In this work, a comparison study between operators using different types circuit presented. The time-registers are implemented TSMC 65nm verified through...

In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. processing, the pulse width of rectangular processing variable. The constructed using basic building blocks such time registers and adders so it characterized by low complexity which can lead to modular versatile design higher-order filters. All were designed verified in TSMC 65 nm technology process. sampling frequency was 5 MHz, gain at frequencies −0.016 dB, cut-off 1.2323 power...

This paper presents a novel time register circuit suitable for time-based or time-domain signal processing. The proposed is based on the capacitor discharging method and compensated against technology process chip temperature variations using calibration loop master-slave approach. contains high-speed comparator simple current-starved inverter logic along with triple-point threshold voltage stabilization loop. designed 28nm Samsung FD-SOI under 1V supply 10MHz operating frequency. Simulation...

In this work, a new current-to-time converter (CDC) based on current-starved inverter is proposed. The time delay of the output pulse edges linearly proportional to control current. benefits proposed topology are simple circuit topology, linear characteristic with positive or negative slope for both rising and falling edges. designed tested using 0.35um CMOS process under 3V supply voltage. linearity error less than 2.1% in range 5nsec delays clock frequency 50MHz.

This research introduces an innovative timemode moving average filter (MAF) tailored for utilization in time-mode signal processing systems. The filter's operational framework is rooted the principles of Finite Impulse Response (FIR) filters. To illustrate its design, three MAF filters comprising by 7, 10, and 13 taps respectively are designed evaluated using a 65nm CMOS process 1.2V supply voltage. A sampling frequency 5MHz employed, accompanied modest current consumption (M+1)9.5μA where M...

In this paper, a wide supply voltage range CMOS VCO ring oscillator is proposed. The core of the consists simple three-stage inverter-based while frequency tuning achieved by modulating gate pMOS transistor. proposed design utilizes an op amp connected as controlled current source that provides reference bias for oscillator, in order to keep internal node stable possible and independent from variations. has been designed 110nm technology 1V up 3.6V at 80MHz. Simulation results over pvt...

A 2.4 GHz digital-controlled oscillator (DCO) based on a novel capacitor tank suitable for all-digital Bluetooth Low Energy (BLE) transmitter is proposed in this paper. The capacitive element which responsible Gaussian Frequency Shift Keying (GFSK) modulation constructed by single nMOS device with simple topology, designed fully depleted silicon insulator (FDSOI) process. can offer capacitance difference the range of few aF constant step. Consequently, it provide accurate linear changes...

This paper proposes a novel circuit of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$z^{-1}$</tex> time-mode programmable multiplier with improved accuracy which can be used as basic building block in filtering and signal processing. The proposed is based on the time register topology employs capacitor discharging approach. built using 28 xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{nm}$</tex> Samsung FD-SOI process...

This paper presents a novel digital to pulse-width converter, designed for the use in time-mode signal processing circuits and systems. The operation principle of proposed converter is based on binary change discharging slope charge-based time register. As design example, 5-bit was implemented using 65nm CMOS process with 1.2V supply voltage. control code applied 5MHz rate, INL error small, full-scale dynamic 44.7dB current consumption 130μA. has great deal potential enhance effectiveness...

In this work, an analog latch is proposed dedicated for the construction of PWM time-mode systems sampled-data signal processing. processing pulse width a rectangular variable. The latching time can be easily programmed lower sampling frequencies without increasing storing capacitor, which leads to smaller chip area compared traditional approach. structure combines advantages and digital systems, it has simple structure, lead modular versatile hierarchy design. All blocks are designed...