In recent years, the advancements in specialized hardware architectures have supported industry and research community to address computation power needed for more enhanced compute intensive artificial intelligence (AI) algorithms applications that already reached a substantial growth, such as natural language processing (NLP) computer vision (CV). The developments of open-source (OSH) contribution towards creation hardware-based accelerators with implication mainly machine learning (ML),...

Abstract Genomic regions that encode small RNA genes exhibit characteristic patterns in their sequence, secondary structure, and evolutionary conservation. Convolutional Neural Networks are a family of algorithms can classify data based on learned patterns. Here we present MuStARD an application learn associated with user-defined sets genomic regions, scan large areas for novel exhibiting similar characteristics. We demonstrate is generic method be trained different classes human loci,...

A significant problem in the field of hardware security consists trojan (HT) viruses. The insertion HTs into a circuit can be applied for each phase chain production. degrade infected circuit, destroy it or leak encrypted data. Nowadays, efforts are being made to address through machine learning (ML) techniques, mainly gate-level netlist (GLN) phase, but there some restrictions. Specifically, number and variety normal circuits that exist free public libraries, such as Trust-HUB, based on few...

Abstract A superharmonic voltage‐controlled injection‐locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz cross‐coupled LC 1.25, 2.5 GHz, is demonstrated. The proposed triple‐band operation achieved by employing novel technique that uses pin‐diodes negative power supply. discrete dividers, built with low noise hetero‐junction FETs high‐frequency SiGe BJTs, are described theoretically while their functionality proven experimentally....

A high-accuracy voltage reference generator is proposed in this paper. It has been designed a CMOS 65 nm technology node, operating with typical supply of 1.2 V, which provides equal to 0.5 V. Measurement results the fabricated chip show variation less than 0.04% over temperature range from −40 125 °C and 0.9% corners. The design demonstrates low noise output good performance under mismatch. current included provide constant current. measured about 1%.

A high-speed dynamic comparator with automatic dc offset compensation is proposed in this paper. The based on a double-tail topology and reduces the by calibration circuit. Avoiding using commonly used capacitive calibration, it can operate at higher speed compared to other topologies. Designed CMOS 65nm technology node, operates 1 V supply voltage clock 10 GHz.

A reconfigurable buck-boost multi-ratio Charge Pump (CP) based on the cross-coupled topology is presented in this paper. The proposed architecture aims to merge different ratios and operation modes one converter. converter able step-up or step-down input voltage at output only by interchanging external connections of circuit. converting up down using conversion achieves higher efficiency levels maximizing power that delivered load. buckboost CP has been designed 65nm TSMC CMOS technology a...

This paper presents a multifunctional circuit realizing the functions of oscillation, mixing, amplification, and frequency multiplication at 5 GHz. A theoretical experimental description is given. The proposed circuit, which combines both injection-locking mixing processes, uses only one port where RF/intermediate signal injection (IS) are applied. IS, used to stabilize subharmonic oscillation (omega <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

SUMMARY An integrated sub‐1V voltage reference generator, designed in standard 90‐nm CMOS technology, is presented this paper. The proposed circuit consists of a conventional bandgap core based on the use p‐n‐p substrate vertical bipolar devices and voltage‐to‐current converter. former produces current with positive temperature coefficient (TC), whereas latter translates emitter‐base device to negative TC. includes two operational amplifiers rail‐to‐rail output stage for enabling stable...

Abstract A 1 V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable for low voltage PLLs. It designed in TSMC 90-nm digital CMOS process and it consists of four switches a current steering configuration, unity gain rail to buffer the sharing effect elimination, one more amplifier minimizing DC mismatch, programmable bias circuitry two drivers based on standard cell XOR gates specific configuration achieving good synchronization between all input pulses at PLL...

This paper presents a novel inductorless dual-mode buck-boost charge pump (CP) based DC-DC converter. The proposed architecture allows the same circuit to accomplish two modes of operation, buck and boost, for degrading or elevating output voltage, respectively, compared input. To achieve each mode, only switching input–output connections is needed without any other modification in design configuration aims merge different functions into one circuit, minimizing time area converter occupies...

In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 μm technology as part of FM (UWBFM) transmitter. The VCO includes current-controlled (CCO) which generates output frequencies between 1.5 and 2.8 GHz voltage-to-current (V-to-I) converter. A frequency doubler based on Gilbert cell, operates weak inversion, doubles the tuning range achieving oscillation 3 5.6 GHz. Thus, well-known proportionality bias current CCOs avoided...

A novel 2.45 GHz RF power harvester has been implemented in a 90 nm standard CMOS process. The proposed architecture reduces the threshold voltage (Vth) by employing pseudo floating-gate (pseudo-FG) new technique and achieves better performance compared with other conventional rectifiers at GHz, without additional fabrication cost. system is initially optimised via matching-boosting circuit, which dominant dual role. Extremely low (−15.43 dBm) signals can be rectified converted to 1.25 V DC.

The 21^st century has been characterized by incredible technological advancements. A key factor of this revolution is the ever-growing circuits complexity that are core components all electronic devices. This resulted in development today's computers but also led to creation a new generation device viruses, called hardware trojans (HTs). HTs can infect leading their degradation, complete destruction, or leakage encrypted information. be inserted into any phase circuit production...

Abstract A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a transmitter. The VCO designed in TSMC 90thinspacenm digital CMOS process and includes Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 5 GHz voltage‐to‐current (V‐to‐I) converter translates input voltage modulation signal to current. Two single‐ended inverter buffers are employed drive either...

This work aims at analyzing three different techniques for synchronizing RF oscillators. These are Injection Locking (ILO), Phase Locked Loop (PLL) and (ILPLL). ILPLL, which is a combination of PLL ILO, has superior noise performance -compared to all the rest- medium frequency offsets same low high offsets. Furthermore, ILPLL better locking range lower phase than ILO phase-shifts close /spl plusmn/90/spl deg/. In this we present two approaches study as show, produce equivalent results...

A CMOS 4× subharmonic mixer (SHM) with an internal phase error correction mechanism operating at mm-wave frequencies is proposed in this paper. The SHM operates a 81-GHz RF input signal and 20-GHz local oscillator (LO) to produce 1-GHz output. single ended converted into octet-phase, through active balun, polyphase filter, certain adders. calibration technique employed, compensate the deviations due circuit mismatches, offering ±5° adjustment between generated shifts. By technique, close...

Summary A USB3.0 compatible transmitter and the linear equalizer of corresponding receiver are presented in this paper. The architecture circuit design techniques used to meet strict requirements overall link explored. Output voltage amplitude de‐emphasis levels programmable, whereas output impedance is calibrated 50Ω. programmable also with its main purpose being compensate for channel losses; employed together a DC offset compensation scheme. 6.25‐GHz provides 10 dB gain equalization...

A dual mode buck-boost charge pump is presented in this paper. The two modes, buck and boost, of the CP can be used by same circuit for degrading or elevating output voltage, respectively, compared to input. Each achieved switching only input-output connections without any other change design DC-DC converter. This configuration aims merge different functions into one minimizing area converter occupies on die. proposed has been designed using TSMC 130nm complementary metal-oxide-semiconductor...

Abstract Subharmonic injection‐locking and self‐oscillating mixing functions of a modified Colpitts oscillator operating at 1 GHz are reported. The circuit, using GaAs FET, is described theoretically experimentally. Phase noise, power consumption conversion gain measurements indicate that the proposed design attractive for low‐cost, low‐power front‐ends. Copyright © 2008 John Wiley &amp; Sons, Ltd.