This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective finite alphabet iterative decoders (NS-FAIDs), exploits the robustness of message-passing LDPC inaccuracies in calculation exchanged messages, and it is shown provide unified framework several previously literature. NS-FAIDs are optimized by density evolution regular irregular codes, different tradeoffs between...

Low-density parity-check (LDPC) code as a very promising error-correction has been adopted the channel coding scheme in fifth-generation (5G) new radio. However, it is challenging to design high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are prone be erroneous. In this article, problem solved gracefully by developing low-complexity check-node update function, greatly improving reliability of check-to-variable messages. By further...

This paper deals with the hardware implementation of recently introduced Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder. The PGDBF is a new type hard-decision decoder for Low-Density Parity-Check (LDPC) code, improved error correction performance thanks to introduction deliberate random perturbation in computing units. In PGDBF, operates during bit-flipping step, objective avoid attraction so-called trapping-sets LDPC code. this paper, we propose an efficient architecture which...

This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: Partially OMS, which performs only partially offset correction, and Imprecise introduces a further level impreciseness in check-node processing unit. We show they allow significant reduction memory (25% with respect to baseline) interconnect, we propose cost-efficient unit architecture, yielding cost 56% baseline. implement FPGA-based layered decoder...

This study evaluates an innovative control approach to assistive robotics by integrating brain–computer interface (BCI) technology and eye tracking into a shared system for mobile augmented reality user interface. Aimed at enhancing the autonomy of individuals with physical disabilities, particularly those impaired motor function due conditions such as stroke, utilizes BCI interpret intentions from electroencephalography signals identify object focus, thus refining commands. integration...

This study introduces an integrated computational environment that leverages Brain-Computer Interface (BCI) technology to enhance information access for individuals with severe disabilities. Traditional assistive technologies often rely on physical interactions, which can be challenging this demographic. Our innovation focuses creating new use novel Human-Computer interfaces provide a more intuitive and accessible experience. The proposed system offers four key applications users controlled...

The Gallager B (GaB), among the hard-decision class of low-density-parity-check (LDPC) algorithms, is an ideal candidate for designing high-throughput decoder hardware. However, GaB suffers from poor error-correction performance. We introduce a probabilistic (PGaB) algorithm that disturbs decisions made during decoding iterations randomly with probability value determined based on experimental studies. propose heuristic switches to PGaB after certain number and show our reduces average...

We propose in this paper a novel approach of adaptive filtering EEG signals. The filter adapts to the intrinsic characteristics each person. goal proposed method is enhance accuracy home devices system controlled by thoughts related two motor imagery actions. μ-rhythm and β-rhythm are specific returned bands that contain information. main idea preserve frequency interest with different value SNR on stop-band. Our experimental results show benefits suitable tuning classifier output system....

This paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework one Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it shown provide unified approach several designs previously literature. NS-FAIDs are optimized by density evolution WiMAX irregular LDPC codes we show they different trade-offs between complexity...

This paper presents an adaptation of the Min-Sum decoders for Low-Density Parity-Check (LDPC) used in enhanced mobile broadband (eMBB) scenario 5th generation networks (5G). Starting from structure proposed LDPC codes 5G where a significant part Variable Nodes (VNs) is with degree-1 and sensitively to be erroneous traditional Offset decoder, we adapt decoding principle decode these codes, targeting improve error correction performance. The named Adapted (AMS), processes core extension parts...

Probabilistic gradient descent bit-flipping (PGDBF) is a hard-decision decoder for low-density parity-check (LDPC) codes, which offers significant improvement in error correction, approaching the performance of soft-information decoders on binary symmetric channel. However, this outstanding known to come with an augmentation complexity, compared non-probabilistic bit flipping (GDBF), becoming drawback decoder. This paper presents new approach implementing PGDBF decoding quasi-cyclic LDPC...

In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. [2], authors show that using randomness in bit-flipping decoders can greatly improve error correction performance. two models random generators proposed and compared through hardware implementation performance simulation. A conventional generator LFSR as a first design, new approach binary sequences produced by decoder, named IVRG, second design. We both performance, while maintaining...

: Brain-computer interface (BCI) control systems monitor neural activity to detect the user's intentions, enabling device through mental imagery. Despite their potential, decoding in real-world conditions poses significant challenges, making BCIs currently impractical compared traditional interaction methods. This study introduces a novel motor imagery (MI) BCI strategy for operating physically assistive robotic arm, addressing difficulties of MI from electroencephalogram (EEG) signals,...

This paper presents a new Bit Flipping (BF) decoder, called the Probabilistic Parallel (PPBF) for Low-Density Parity-Check (LDPC) codes on Binary Symmetric Channel.In PPBF, flipping operation is performed in probabilistic manner which shown to improve significantly error correction performance.The advantage of PPBF also comes from fact that no global computation required during decoding process and all computations can be executed local computing units in-parallel.The provides considerable...

This paper presents a new embedded architecture for home devices control system directed through motor imagery actions captured by EEG headset. The proposed is validated an offline approach which consists on using available public data-set. These recording are always accompanied with noise and useless information related to the equipment, eyes blinking many others resources of artifacts. For this reason, complex signal processing required; starting filtering keep frequency interest located...

This paper presents a new high-throughput, low-complexity Bit Flipping (BF) decoder for Low-Density Parity-Check (LDPC) codes on the Binary Symmetric Channel (BSC), called Probabilistic Parallel (PPBF). The advantage of PPBF comes from fact that, no global operation is required during decoding process and all computations could be parallelized localized at computing units. Also in PPBF, probabilistic feature flipping Variable Node (VN) incorporated satisfaction level its CN neighbors. type...

SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations, and need be hardened insure correct running. To validate any fault tolerant solution for these SRAM-FPGA, injection campaigns must conducted carefully. In this work, we present a new design flow perform localized internal on specific parts of Design Under Test (DUT). achieve this, combine between 1) Partial Dynamic Reconfiguration (PDR) via Internal Configuration Access Port (ICAP) rapid insertion SRAM;...

Brain–computer interfaces (BCIs) have the potential to enable individuals interact with devices by detecting their intention from brain activity. A common approach BCI is decode movement motor imagery (MI), mental representation of an overt action. However, research-grade electroencephalogram (EEG) acquisition a high number sensors are typically necessary achieve spatial resolution required for reliable analysis. This entails monetary and computational costs that make these approaches...

Performance of LDPC decoders at high SNR is dominated by trapping sets that induce an error floor in the performance curve. We propose a new algorithm resolves and lowers floor. The algorithm, called Syndrome Bit Flipping (SBF), computes sum adjacent parity violations each symbol node. Bits are flipped comparing syndrome against time-varying threshold decoding key. SBF compared to other bit-flipping on Binary Symmetric Channel (BSC), demonstrated as post-processing step for Noisy Gradient...

Brain-computer interfaces can be used to operate devices by detecting a person's intention from their brain activity. Decoding motor imagery (MI) electroencephalogram (EEG) signals is commonly approach for this purpose. To reliably identify MI EEG signals, sufficient number of sensors usually required. However, large increases the computational cost discriminating classes. Furthermore, consumer-grade that measure often employ reduced compared medical- or research-grade devices. In...

In the recent literature, study of iterative LDPC decoders implemented on faulty-hardware has led to counter-intuitive conclusion that noisy could perform better than their noiseless version. This peculiar behavior been observed in finite codeword length regime, where noise perturbating decoder dynamics help escape attraction fixed points such as trapping sets. this paper, we will two recently introduced derived from versions gradient descent bit-flipping (GDBF). Although GDBF is known be a...

Sensorimotor rhythms (SMRs) caused by motor imagery are key issues for subject with severe disabilities when controlling home devices. However, the development of such EEG-based control system requires a great effort to reach high accuracy in real-time. Furthermore, BCIs have confront inter-individual variability, imposing parameters methods be adapted each subjects. In this paper, we propose novel solution classify right and left hands(RH LH) thoughts. Our approach integrates adaptive...