A5075892935- Parallel Computing and Optimization Techniques
- Advanced Data Storage Technologies
- Cloud Computing and Resource Management
- Low-power high-performance VLSI design
- Distributed systems and fault tolerance
- Distributed and Parallel Computing Systems
- Radiation Effects in Electronics
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- IoT and Edge/Fog Computing
- Caching and Content Delivery
- Interconnection Networks and Systems
- Green IT and Sustainability
- Fault Detection and Control Systems
- Blockchain Technology Applications and Security
- Energy Efficient Wireless Sensor Networks
Institute for Independent Studies Zürich
2024
Queen's University Belfast
2017-2022
In this paper, we present the results of our comprehensive measurement study timing and voltage guardbands in memories cores a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, reveal how adopted margins vary among 8 CPU chip, 3 different sigma chips show prone they are to worst-case noise. addition, characterize variation 'weak' DRAM cells terms their retention time across 72 evaluate error mitigation efficacy available error-correcting codes case operation under...
The aggressive scaling of technology may have helped to meet the growing demand for higher memory capacity and density, but has also made DRAM cells more prone errors. Such a reality triggered lot interest in modeling behavior either predicting errors advance or adjusting circuit parameters achieve better tradeoff between energy efficiency reliability. Existing efforts studied impact few operating temperature on reliability using custom FPGAs setups, however they neglected combined effect...
The explosive growth of Internet-connected devices will soon result in a flood generated data, which increase the demand for network bandwidth as well compute power to process data. Consequently, there is need more energy efficient servers empower traditional centralized Cloud data-centers emerging decentralized at Edges Cloud. In this paper, we present our approach, aims developing new class micro-servers - UniServer that exceed conservative and performance scaling boundaries by introducing...
The explosive growth of data increases the storage needs, especially within servers, making DRAM responsible for more than 40% total system power. Such a reality has made researchers focus on energy saving schemes that relax pessimistic circuit parameters at cost potential faults. In an effort to limit resultant risk critical disruption, new methods were introduced split into domains with varying reliability and benefits such may have been showcased simulators but neither implemented real...
The main memory in today's systems is based on DRAMs, which may offer low cost and high density storage for large amounts of data but it comes with a drawback; DRAM cells need to be refreshed frequently retaining the stored data. refresh rate modern DRAMs set worst-case retention time without considering access statistics, thereby resulting very frequent operations. Such leads eventually power performance overheads, are increasing higher densities. However, such rates not even required due...
We are witnessing an explosive growth in the number of Internet-connected devices and emergence several new classes Internet Things (IoT) applications that require rapid processing abundance data. To overcome resulting need for more network bandwidth low latency, a paradigm has emerged promotes offering Cloud services at Edge, closer to users. However, Edge is highly constrained environment with limited power budget servers per installation which, turn, limits devices, such as sensors, can...
Improving energy efficiency of the memory subsystem becomes increasingly important for all digital systems due to rapid growth data. Many recent schemes have attempted reduce DRAM power by relaxing refresh rate, which may negatively affect reliability. To optimize trade-offs between and reliability, existing studies rely on experimental setups based FPGAs use few known data-patterns exciting rare worst-case circuit reliability effects. However, doing so, be missing capture real behavior...
Today's rapid generation of data and the increased need for higher memory capacity has triggered a lot studies on aggressive scaling refresh period, which is currently set according to rare worst case conditions. Such analysed in detail data-dependent circuit level factors indicated online DRAM characterization due variable cell retention time. They have done so by executing few test patterns FPGAs under controlled temperatures using thermal testbeds, however cannot be available field....
In this paper, we present the implementation of a heterogeneous-reliability DRAM framework, Shimmer, on commodity server with fully fledged OS. Shimmer enables splitting into multiple domains varying reliability and allocation data depending their criticality. Compared to existing studies which use simulators, consider practical restrictions stemming from real hardware investigate methods overcome them. particular, reveal that memory framework requires disabling interleaving, results in...
The garbage collector (GC) is a crucial component of language runtimes, offering correctness guarantees and high productivity in exchange for run-time overhead. Concurrent collectors run alongside application threads (mutators) share CPU resources. A likely point contention between mutators GC and, consequently, potential overhead source the shared last-level cache (LLC).
With the increase in compute nodes large platforms, a proportional node failures will follow. Many application-based checkpoint/restart (C/R) techniques have been proposed for MPI applications to target reduced mean time between failures. However, rollback as part of recovery remains dominant cost even highly optimised employing C/R techniques. Continuing execution past checkpoint (that is, reducing rollback) is possible message-passing runtimes, but extremely complex design and implement....
Power consumption and reliability of memory components are two the most important hurdles in realizing exascale systems. Dynamic random access (DRAM) scaling projections predict significant performance power penalty due to conventional use pessimistic refresh periods catering for worst-case cell retention times. Recent approaches relax those rates only on ``strong'' cells, or build application-specific error resilience data placement. However, these cannot reveal full potential a relaxed...
In recent years, there has been a growing interest on relaxing the pessimistic DRAM refresh rate due to incurred power and throughput loss. Undeniably, critical factor in determining relaxation that can be achieved lies degree of error-rate deterioration is amount estimated errors handled by system mitigation schemes which are mainly being evaluated simulators. To estimate faults under relaxed refresh, majority existing works rely failure probability models using only spatial distribution...
Improving the energy efficiency of DRAMs becomes very challenging due to growing demand for storage capacity and failures induced by manufacturing process. To protect against failures, vendors adopt conservative margins in refresh period supply voltage. Previously, it was shown that these are too pessimistic will become impractical high-power costs, especially future DRAM technologies. In this article, we present a new technique automatic scaling under reduced voltage minimizes probability...
The aggressive scaling of technology may have helped to meet the growing demand for higher memory capacity and density, but has also made DRAM cells more prone errors. Such a reality triggered lot interest in modeling behavior either predicting errors advance or adjusting circuit parameters achieve better trade-off between energy efficiency reliability. Existing efforts studied impact few operating temperature on reliability using custom FPGAs setups, however they neglected combined effect...