A5062849403- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- Low-power high-performance VLSI design
- Advanced Data Storage Technologies
- Cloud Computing and Resource Management
- Advanced Vision and Imaging
- Radiation Effects in Electronics
- Video Coding and Compression Technologies
- Distributed and Parallel Computing Systems
- Robotics and Sensor-Based Localization
- Advanced Data Compression Techniques
- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and FPGA Design Techniques
- Robotic Path Planning Algorithms
- VLSI and Analog Circuit Testing
- Error Correcting Code Techniques
- Distributed systems and fault tolerance
- Image Processing Techniques and Applications
- IoT and Edge/Fog Computing
- Multimedia Communication and Technology
- CCD and CMOS Imaging Sensors
- Advanced Image Processing Techniques
University of Thessaly
2015-2024
Centre for Research and Technology Hellas
2015-2017
Instituto de Telecomunicações
2012
University of Coimbra
2012
Motorola (United States)
2000-2008
Northwestern University
2006
Embedded Systems (United States)
2006
University of Illinois Urbana-Champaign
1996-2003
The problem of automatically generating hardware modules from a high level representation an application has been at the research forefront in last few years. In this paper, we use OpenCL, industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our architectural synthesis tool, SOpenCL (Silicon-OpenCL), adapts OpenCL into novel design flow which efficiently maps coarse fine-grained parallelism onto FPGA reconfigurable fabric. is...
Dependable computing on unreliable substrates is the next challenge community needs to overcome due both manufacturing limitations in low geometries and necessity aggressively minimize power consumption. System designers often need analyze way hardware faults manifest as errors at architectural level how these affect application correctness. This paper introduces GemFI, a fault injection tool based cycle accurate full system simulator Gem5. GemFI provides methods easily extensible support...
In this paper we propose a technique that uses an additional mini cache located between the I-Cache and CPU core, buffers instructions are nested within loops continuously otherwise fetched from I-Cache. This mechanism is combined with code modifications, through compiler, greatly simplify required hardware, eliminate unnecessary instruction fetching, consequently reduce signal switching activity dissipated energy.
Article Using dynamic cache management techniques to reduce energy in a high-performance processor Share on Authors: Nikolaos Bellas Department of Electrical & Computer Engineering and the Coordinated Science Laboratory, University Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL ILView Profile , Ibrahim Hajj Constantine Polychronopoulos Authors Info Claims ISLPED '99: Proceedings 1999 international symposium Low power electronics designAugust Pages...
Energy dissipated in on-chip caches represents a substantial portion the energy budget of today's processors. Extrapolating current trends, this is likely to increase near future, since devices devoted occupy an increasingly larger percentage total area chip. We extend work proposed by J. Kin et al. (1997), which extra, small cache (called filter cache) inserted between CPU data path and L1 serves most references initiated from CPU. In our scheme, compiler used generate code that exploits...
Several applications may trade-off output quality for energy efficiency by computing only an approximation of their output. Current approaches to software-based approximate often require the programmer specify parts code or data structures that can be approximated. A largely unaddressed challenge is how automate analysis significance quality. To this end, we propose a methodology and toolset automatic analysis. We use interval arithmetic algorithmic differentiation in our profile-driven yet...
In this paper, we focus on low-power design techniques for high-performance processors at the architectural and compiler levels. We mainly developing methods reducing energy dissipated in on-chip caches. Energy caches represents a substantial portion budget of today's processors. Extrapolating current trends, is likely to increase near future, since devices devoted occupy an increasingly larger percentage total area chip. propose method that uses additional minicache located between I-Cache...
CPUs typically operate at a voltage which is higher than what strictly required, using margins to account for process variability and anticipate any combination of adverse operating conditions. However, these worst-case scenarios occur rarely, if ever, thus the overly pessimistic resulting in excessive power dissipation leads decreased performance under capping. In this paper, we investigate impact reducing beyond nominal level on efficiency CPU capping mechanisms, three commercial systems,...
We introduce Fluidity, a framework enabling the flexible and adaptive deployment of serverless modular applications in systems comprising cloud, edge, mobile nodes. Based on declarative description application requirements, custom placement policy, formal system infrastructure description, Fluidity plans executes an initial components cloud–edge-mobile continuum. Furthermore, at runtime, monitors resource availability position nodes, adapts accordingly, without any manual intervention from...
Fisheye lenses are often used in scientific or virtual reality applications to enlarge the field of view a conventional camera. lens distortion correction is an image processing application which transforms distorted fisheye images back natural-looking perspective space. This characterized by non-linear streaming memory access patterns that make main bandwidth key performance limiter. We have developed system on custom board includes Xilinx Virtex-4 FPGA. express high level language, and we...
We introduce a task-based programming model and runtime system that exploit the observation not all parts of program are equally significant for accuracy end-result, in order to trade off quality outputs increased energy-efficiency. This is done structured flexible way, allowing easy exploitation different points quality/energy space, without adversely affecting application performance. The can apply number policies decide whether it will execute less-significant tasks accurately or...
The proliferation of heterogeneous computing platforms presents the parallel community with new challenges. One such challenge entails evaluating efficacy architectures and identifying architectural innovations that ultimately benefit applications. To address this challenge, we need benchmarks capture execution patterns (i.e., dwarfs or motifs) applications, both present future, in order to guide future hardware design. Furthermore, desire a common programming model for facilitates code...
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based system on chip (SoC) that meet applications requirements. The designer can customize by selecting from large number of pre-defined peripherals fixed IP functions providing new hardware, typically expressed using RTL. Hardware accelerators application-specific extensions to computational capabilities is an efficient mechanism enhance performance reduce power dissipation. What missing integrated...
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based system on chip (SoC) that meet applications requirements. The designer can customize by selecting from large number of pre-defined peripherals fixed IP functions providing new hardware, typically expressed using RTL. Hardware accelerators application-specific extensions to computational capabilities is an efficient mechanism enhance performance reduce power dissipation. What missing integrated...
Hardware designers and engineers typically need to explore a multi-parametric design space in order find the best configuration for their designs using simulations that can take weeks months complete. For example, of special purpose chips parameters such as optimal bit width data representation. This is case development complex algorithms Low-Density Parity-Check (LDPC) decoders used modern communication systems. Currently, high-performance computing offers wide set acceleration options,...
Multi-core Application Specific Instruction Processors (ASIPs) are increasingly used in multimedia applications due to their high performance and programmability. Nonetheless, efficient use requires extensive modifications the initial code order exploit features of underlying architecture. In this paper, through example implementing Advance Video Coding (AVS) a heterogeneous dual-core SIMD processor, we present guide developers who wish perform task-level decomposition any video decoder...
The memory hierarchy of high-performance and embedded processors has been shown to be one the major energy consumers. For example, Level-1 (L1) instruction cache (I-Cache) StrongARM processor accounts for 27% power dissipation whole chip, whereas fetch unit (IFU) I-Cache Intel's Pentium Pro are single most important consuming modules with 14% total [2]. Extrapolating current trends, this portion is likely increase in near future, since devices devoted caches occupy an increasingly larger...
Wide-angle (fisheye) lenses are often used in virtual reality and computer vision applications to widen the field of view conventional cameras. Those lenses, however, distort images. For most real-world video stream needs be transformed, at real-time (20 frames/sec or better), back natural-looking, central perspective space. This paper presents implementation, optimization characterization a fisheye lens distortion correction application on three platforms: conventional, homogeneous...
The explosive growth of Internet-connected devices will soon result in a flood generated data, which increase the demand for network bandwidth as well compute power to process data. Consequently, there is need more energy efficient servers empower traditional centralized Cloud data-centers emerging decentralized at Edges Cloud. In this paper, we present our approach, aims developing new class micro-servers - UniServer that exceed conservative and performance scaling boundaries by introducing...
We introduce a task-based programming model and runtime system that exploit the observation not all parts of program are equally significant for accuracy end-result, in order to trade off quality outputs increased energy-efficiency. This is done structured flexible way, allowing easy exploitation different points quality/energy space, without adversely affecting application performance. The can apply number policies decide whether it will execute less-significant tasks accurately or...
To improve power efficiency, researchers are experimenting with dynamically adjusting the voltage and frequency margins of systems to just above minimum required for reliable operation. Traditionally, manufacturers did not allow reducing these margins. Consequently, existing studies use system simulators, or software fault-injection methodologies, which slow, inaccurate cannot be applied on realistic workloads. However recent CPUs operation outside nominal voltage/frequency envelope. We...
The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric space exploration optimization, followed by verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth data representation, through time-consuming Monte Carlo simulations. A prominent example this simulation-based process the decoders error correcting systems, Low-Density Parity-Check (LDPC) codes...
Visual Simultaneous Localization and Mapping (vSLAM) is the method of employing an optical sensor to map robot’s observable surroundings while also identifying pose in relation that map. The accuracy speed vSLAM calculations can have a very significant impact on performance effectiveness subsequent tasks need be executed by robot, making it key building component for current robotic designs. application area humanoid robotics particularly difficult due unsteady locomotion. This paper...